Search - pipeline

[OS Develop] fifo

Description: 一个使用匿名管道进行通信的示例程序，重点是管道是单向的，进行读写需要建立两个管道。-A pipeline to carry out the use of anonymous communications sample programs, with a focus on pipeline is one-way, to read and write need to build two pipelines.
Platform: | Size: 2048 | Author: lht | Hits:

[SCSI-ASPI] dlx_verilog

Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
Platform: | Size: 9216 | Author: 李乔 | Hits:

[Software Engineering] bp

Description: 本书涉及的研究方法主要应用于油田生产的实际工作中，包括一般储层参数预测、薄互油藏参数预测、火山岩储层参数预测和储层随机模拟等问题，同时还涉及了石油工业中的油管缺损检测、海底输油管道腐蚀检测等应用问题，对污水处理絮凝过程的智能优化控制及移动机器人的全局和局部路径规划等问题的应用也进行了一定的研究。-Book of research methods involved are mainly used in oil field production of practical work, including the general prediction of reservoir parameters, thin reservoir parameter prediction, volcanic prediction of reservoir parameters and reservoir stochastic simulation and other issues, but also involved in the oil industry pipeline defect detection, submarine detection applications such as pipeline corrosion problem of the sewage treatment process of flocculation and optimal control of intelligent mobile robot path planning global and local issues such as the application have also been some study.
Platform: | Size: 15801344 | Author: cheny | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPS

Description: mips处理器指令仿真器，可查看流水线执行方式-mips instruction processor emulator, you can review the pipeline implementation
Platform: | Size: 991232 | Author: 魏继增 | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧-About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
Platform: | Size: 1028096 | Author: JET | Hits:

[VHDL-FPGA-Verilog] FIFO_8_8

Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Platform: | Size: 5120 | Author: 镜子 | Hits:

[Program doc] Pipeline_FFT

Description: Description of a pipeline architecture for a FFT processor, based on the R22SDF algorithm.
Platform: | Size: 194560 | Author: rhadookoo | Hits:

[JSP/Java] Pipeline

Description: java写的关于流水线工作过程的模拟程序-java to write the work on the assembly line process simulation program
Platform: | Size: 15360 | Author: xiajing | Hits:

[VHDL-FPGA-Verilog] float_data_multiple_use_fixed_pipeline_verilog_pro

Description: 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！-a program of float multiply, using 3-stage pipeline technology
Platform: | Size: 1024 | Author: xietianjiao | Hits:

[VHDL-FPGA-Verilog] add

Description: 流水线乘法器与加法器开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Platform: | Size: 1024 | Author: 来法旧佛 | Hits:

[Special Effects] GPUGems1

Description: GPU Gems is a compilation of articles covering practical real-time graphics techniques arising from the research and practice of cutting-edge developers. It focuses on the programmable graphics pipeline available in todays graphics processing units (GPUs) and highlights quick and dirty tricks used by leading developers, as well as fundamental, performance-conscious techniques for creating advanced visual effects. The contributors and editors, collectively, bring countless years of experience to enlighten and propel the reader into the fascinating world of programmable real-time graphics.
Platform: | Size: 14535680 | Author: mike | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPS

Description: 带分支预测的MIPS流水线的verilog原代码。详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Platform: | Size: 17408 | Author: 张鹤 | Hits:

[MiddleWare] Pipeline

Description: 计算各油井到主管道之间的输油管道最小长度总和。-Pipeline
Platform: | Size: 1024 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] waterline_adder

Description: 这是一个用Verilog编写的四级流水线加法器-This is a Verilog prepared with four pipeline adder
Platform: | Size: 1024 | Author: 伊莲幽梦 | Hits:

[Windows Develop] CPU_verilog

Description: 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
Platform: | Size: 63488 | Author: xq | Hits:

[DSP program] pipe

Description: This an example of pipeline implemented in SystemC-This is an example of pipeline implemented in SystemC
Platform: | Size: 12288 | Author: Rachel Zhang | Hits:

[OpenGL program] Fire

Description: firestarter – A Real-Time Fire Simulator Many obstacles exist in attempting to graphically render physical phenomena that are highly fluid and ostensibly chaotic in nature. Fire is a prime example of such phenomena. Given the unrealizable computational complexity of chemical-atomic modeling, this paper explores how to best apply our current understanding of the physical fire model to balance computational stresses for optimal realism. Special emphasis is given specifically to the constraints imposed by real-time rendering, as opposed to production pipeline rendering, introducing firestarter – a real-time fire simulator developed by the author using OpenGL – which features some unique implementations of previously discussed topics.
Platform: | Size: 1404928 | Author: hwind | Hits:

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[OS Develop] fifo

[SCSI-ASPI] dlx_verilog

[Software Engineering] bp

[ARM-PowerPC-ColdFire-MIPS] MIPS

[VHDL-FPGA-Verilog] pipeline

[VHDL-FPGA-Verilog] FIFO_8_8

[Program doc] Pipeline_FFT

[JSP/Java] Pipeline

[VHDL-FPGA-Verilog] float_data_multiple_use_fixed_pipeline_verilog_pro

[VHDL-FPGA-Verilog] add

[Special Effects] GPUGems1

[ARM-PowerPC-ColdFire-MIPS] MIPS

[MiddleWare] Pipeline

[VHDL-FPGA-Verilog] waterline_adder

[Windows Develop] CPU_verilog

[DSP program] pipe

[OpenGL program] Fire

[VHDL-FPGA-Verilog] cordic

[Windows Develop] pipe3

[VHDL-FPGA-Verilog] fir_512_378_mux

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