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Description: verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
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Size: 915456 |
Author: 陈祥 |
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Description: 实现LINUX 经典流水线算法。 PIPELINE，即将各个工作阶段插入链表，下一个的输入，依赖于上一个的输出-Achieve LINUX classic lines algorithms. PIPELINE, each session is about to insert the list, the next input, the output depends on the previous one
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Size: 1024 |
Author: 杨帆 |
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Description: Windows下，匿名管道通信
VC6环境-pipeline communicate
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Size: 6660096 |
Author: zhang |
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Description: 使用VERILOG實現MIPS2000的PIPELINE-Use VERILOG realized MIPS2000 the PIPELINE
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Size: 2048 |
Author: opgp |
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Description: 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.
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Size: 4096 |
Author: yefeng |
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Description: Enchanged pipeline monitoring with fiberoptic
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Size: 74752 |
Author: gokhan |
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Description: 用图形界面演示模型机的指令序列在5级流水线上的执行过程。使用高级语言Java，在Eclipse环境下开发流水线的仿真程序。实现针对任意的无相关模型机指令序列（包括数据前推、load前推并解决控制相关），能单步显示出每个时钟周期流水线上指令的执行情况，具体包括：时钟周期及编号、各级流水线寄存器的内容、各级流水线的控制信号。-
Graphical interface demo model machine instruction sequence is d on five pipeline. Using high-level languages Java, Eclipse development environment in the pipeline simulation program. Achieve no correlation model for any sequence of machine instructions (including data before pushing, pushing and resolved before the load control related), to show the implementation of a single step on each clock cycle instruction pipeline, including: number of clock cycles and each content-stage pipeline registers, control signal line levels.
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Size: 26624 |
Author: 孙雅楠 |
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Description: Water Pipeline Full Excel Design with Comparison with Oil
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Size: 731136 |
Author: Chukwuemeka |
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Description: 经典三维漏磁检测模型，管道漏磁检测模型，网格已划分，结果正确，希望帮到初学者们。-Classic 3-d model of magnetic flux leakage testing, pipeline magnetic flux leakage testing model, the grid is divided, the result is correct, hope to help beginners.
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Size: 1024 |
Author: 张玉祥 |
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Description: 关于城市输油管道的博弈论分析，采用纳什均衡等博弈理论进行分析-Game theory on urban pipeline analysis, using game theory Nash equilibrium were analyzed
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Size: 1247232 |
Author: Duan Anqi |
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Description: 流水线部分模块，流水线寄存器的实现，ex级-Assembly line part of the module, pipeline register
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Size: 177152 |
Author: maomao |
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Description: C语言黑客编程[6] -零管道主动连接型后门的编写-C programming language hacker [6] - zero pipeline active connection type of write back door
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Size: 5020672 |
Author: Steven |
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Description: 基于 G I S 组件的地下管线系统的
设计与实现-Pipeline cross-section analysis documents, concepts, algorithms, etc.
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Size: 268288 |
Author: 罗 |
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Description: 提供了十几种GStreamer的pipeline，所有的pipeline都亲测过，GStreamer版本1.0-Provides a dozen GStreamer pipeline, all the pipeline are measured, GStreamer version 1.0
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Size: 17408 |
Author: 胡啸天 |
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Description: Face Pipeline to view and see the image features
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Size: 2048 |
Author: fahad123
|
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Description: Pressure Calculation for pipeline
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Size: 113664 |
Author: zura
|
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Description: Auto-filling of Summary Result Tables of Offshore Pipeline A&R and Normal Laying Analysis using MATLAB
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Size: 327680 |
Author: zaragooza |
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Description: 1. understand how to improve CPU performance
2. master the working principle of pipelined MIPS microprocessor.
3. understand the concept of data adventure, control risk and the solution of pipeline conflict.
4. mastering the testing method of pipelined MIPS microprocessor(this file contains 3 packs,which is developed in Xilinx ISE
contain the basic functions of a typical CPU
5 stages:IF,ID,EX,MEM,WB
for education only)
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Size: 633856 |
Author: D.FRANCIS |
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Description: 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
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Size: 14336 |
Author: Si Cheng |
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Description: pipeline ADC simulink
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Size: 2412544 |
Author: 二da王 |
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