This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.

流水线源文件\adder.v
............\adder4.v
............\alu16.v
............\ALU_control.v
............\control_new.v
............\cpu.bdf
............\cpu.vwf
............\Data_mem.v
............\EXMEM.v
............\IDEX.v
............\IFID.v
............\ins.txt
............\Ins_mem.v
............\ins_qs.txt
............\jal.v
............\maoxian.v
............\MEMWB.v
............\mux3.v
............\Mux32_2.v
............\Mux32_4.v
............\Mux5.v
............\mux_2.v
............\PC.v
............\Registers.v
............\same.v
............\sign_extend.v
............\sign_extend2.v
............\sl2.v
............\sll2.v
............\zhuanfa.v
............\说明.txt
流水线源文件

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