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[Documents] PCI

Description: EDA与PLD基于FPGA的PCI总线接口设计-PLD EDA and FPGA-based PCI bus interface
Platform: | Size: 1024 | Author: 张慧 | Hits:

[Other Riddle games] RGB

Description: PLDVGA显示，可以显示四种状态，俄罗斯方块-PLDVGA Show
Platform: | Size: 545792 | Author: 丁卯 | Hits:

[VHDL-FPGA-Verilog] PLD_Programmable_Logic_Devices

Description: 可编程逻辑器件PLD Programmable Logic Devices不错的资料-Programmable logic devices PLDPLD Programmable Logic Devices good information
Platform: | Size: 1034240 | Author: c | Hits:

[VHDL-FPGA-Verilog] Lab01

Description: 快速熟悉ISE软件的使用，适合初学者，是一系列小操作流程的集合。-To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD circuits To become familiar with using Xilinx ISE to write HDL representations of PLD circuits To become familiar with using Xilinx ISE to write HDL testbench simulations of PLD circuits To become familiar with downloading PLD circuits to the Nexys development board
Platform: | Size: 1250304 | Author: 飞飞三号 | Hits:

[Embeded-SCM Develop] pld_classic_hardware_development_programming_langu

Description: pld classic hardware development programming language modelsim tutorialpld硬件开发编程语言modelsim经典教程-pld classic hardware development programming language modelsim tutorialpld classic hardware development programming language modelsim tutorial
Platform: | Size: 505856 | Author: 海燕 | Hits:

[Embeded-SCM Develop] BGA

Description: 随着可编程器件(PLD) 密度和I/O 引脚数量的增加，对小封装和各种封装 形式的需求在不断增长。球栅阵列(BGA) 封装在器件内部进行I/O 互联， 提高了引脚数量和电路板面积比，是比较理想的封装方案。在相同面积 上，典型的BGA 封装互联数量是四方扁平(QFP) 封装的两倍。而且，BGA 焊球要比QFP 引线强度高的多，可靠的封装能够承受更强的冲击。 Altera 为高密度PLD 用户开发了高密度BGA 解决方案。这种新的封装形 式占用的电路板面积不到标准BGA 封装的一半。 本应用笔记旨在帮助您完成Altera 高密度BGA 封装的印刷电路板(PCB) 设计，并讨论： ■ BGA 封装简介 ■ PCB 布板术语 ■ 高密度BGA 封装PCB 布板-As programmable logic devices (PLDs) increase in density and I/O pins, the demand for small packages and diverse packaging options continues to grow. Ball-grid array (BGA) packages are an ideal solution because the I/O connections are on the interior of the device, improving the ratio between pin count and board area. Typical BGA packages contain up to twice as many connections as quad flat pack (QFP) packages for the same area. Further, BGA solder balls are considerably stronger than QFP leads, resulting in robust packages that can tolerate rough handling. Altera has developed high-density BGA solutions for users of high-density PLDs. These new formats require less than half the board space of standard BGA packages. This application note provides guidelines for designing your printed circuit board (PCB) for Altera’s high-density BGA packages and discusses: ■ Overview of BGA Packages ■ PCB Layout Terminology ■ PCB Layout for High-Density BGA Packages
Platform: | Size: 391168 | Author: acermouse | Hits:

[matlab] PID

Description: pld程序，学习一下，希望对各位大侠有用-pld program, learning about, hope you heroes helpful
Platform: | Size: 219136 | Author: 马百杰 | Hits:

[VHDL-FPGA-Verilog] PLDyuDSP

Description: 基于PLD的DSP设计方案，应用论文，有硬件语言支持。-DSP
Platform: | Size: 120832 | Author: 扬威 | Hits:

[DSP program] DSP_design_classic_PLD_Developmen_Information

Description: DSP design classic PLD Development Information PLD 开发DSP设计方案经典资料-DSP design classic PLD Development Information
Platform: | Size: 120832 | Author: 81 | Hits:

[VHDL-FPGA-Verilog] top

Description: PLD大赛 扫频仪的verilog源码，实现了数字鉴幅鉴相功能，很有参考价值-PLD Series Sweep of the verilog source code, to achieve the digital Kam amplitude phase function, a good reference
Platform: | Size: 10312704 | Author: 刘耀 | Hits:

[JSP/Java] asd

Description: 一套物流管理系统，其中用到了数据库，文档是于格式的，希望对各位朋友有帮助；-A logistics management system, which uses a database, the document was pld format, hope to help our friends
Platform: | Size: 1829888 | Author: 风不 | Hits:

[VHDL-FPGA-Verilog] LED.Control

Description: 发光二极管控制 利用LP-2900实验仪Altera模块上的PLD器件，以“流水灯”形式点亮A区的L1～L12共12个发光二极管，即使这12个发光二极管周期性地按照1秒的间隔从左向右依次循环点亮。要求用VHDL语言实现。仿真出控制12位发光二极管依次循环点亮的波形。-LED Control
Platform: | Size: 30720 | Author: duopk | Hits:

[VHDL-FPGA-Verilog] LED.dot.matrix.display

Description: LED点阵显示器 利用LP-2900实验仪Altera模块上的PLD器件，编写VHDL程序，设计一个扫描控制电路，在H区的8*8型LED点阵上实现点阵的逐点显示，扫描显示的顺序是光点从左上角像素点开始，终止于右下角像素点，然后周而复始地重复运行下去。扫描全部区域大概所需时间为13s。-LED dot matrix display
Platform: | Size: 80896 | Author: duopk | Hits:

[VHDL-FPGA-Verilog] FIFO2

Description: 可编程逻辑设计器件（PLD）自推出以来解决了实验室电路板的开发周期问题，该程序实现了FIFO的设计！-Programmable logic design devices (PLD) to solve the laboratory since its launch the development cycle of the circuit board, the program implements the FIFO design!
Platform: | Size: 6144 | Author: 张雨朋 | Hits:

[SCM] PLD

Description: 实现路口交通灯系统的控制方法很多，可以用标准逻辑器件、可编程序控制器和单片机等方案来实现-To achieve control of intersection traffic signal systems are many ways you can use the standard logic devices, programmable logic controllers and other programs to achieve SCM
Platform: | Size: 57344 | Author: 王大富 | Hits:

[matlab] ABEL_PLD_Tips

Description: ABEL PLD编程笔记 ABEL PLD编程笔记-ABEL PLD programming notes ABEL PLD programming notes ABEL PLD programming notes
Platform: | Size: 157696 | Author: augusdi | Hits:

[VHDL-FPGA-Verilog] clock-synchronized-registers

Description: 一般来说，CPU的读写时钟会引入到PLD中，笔者利用CPU的读写时钟实现同步读写寄存器，提高设计的可靠性。因此这种建模方式是推荐的CPU读写PLD寄存器建模方式-In general, CPU clock will read and write the introduction to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve design reliability. This modeling approach is therefore recommended to read and write CPU registers modeling methods PLD
Platform: | Size: 90112 | Author: 李拉 | Hits:

[VHDL-FPGA-Verilog] Max_Plus_II-_tutorial

Description: Max+plusII(或写成Maxplus2,或MP2) 是Altera公司推出的的第三代PLD开发系统(Altera第四代PLD开发系统被称为：QuartusII，主要用于设计新器件和大规模CPLD/FPGA).使用MAX+PLUSII的设计者不需精通器件内部的复杂结构。设计者可以用自己熟悉的设计工具（如原理图输入或硬件描述语言）建立设计，MAX+PLUSII把这些设计转自动换成最终所需的格式。其设计速度非常快。Maxplus2被公认为是最易使用，人机界面最友善的PLD开发软件，特别适合初学者使用。 -Max+ plusII (or written Maxplus2, or MP2) is Altera' s third generation introduced PLD development system (Altera fourth-generation PLD development system is called: QuartusII, mainly for the design of new devices and large-scale CPLD/FPGA) . using the MAX+ PLUSII designers do not need to master the complexity of the internal structure of the device. Designers can use familiar design tools (such as schematic or hardware description language) to establish the design, MAX+ PLUSII automatically turn these designs into the final desired format. The design speed is very fast. Maxplus2 is recognized as the most easy to use, the most friendly man-machine interface PLD development software, especially for beginners.
Platform: | Size: 89088 | Author: myf | Hits:

[VHDL-FPGA-Verilog] 2

Description: EDA的课程设计，利用VHDL语言、PLD设计基于FPGA的出租车计费系统，选用ALTERA公司低功耗、低成本、高性能的FPGA芯片EPF10K10，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了编译，功能仿真和下载。使其实现计费以及预置和模拟汽车启动、加速、停止、暂停等功能，并动态扫描显示车费数目。-EDA curriculum design, the use of VHDL language, PLD design FPGA-based taxi billing system, the company selected ALTERA low power, low-cost, high-performance FPGA chip EPF10K10, the MAX+ PLUS Ⅱ software as a development platform, design a taxi billing system and make the compilation process, functional simulation, and download. To achieve automotive billing and pre-and simulation start, accelerate, stop, pause and other functions, and the number of dynamic scans indicate the fare.
Platform: | Size: 8192 | Author: wang | Hits:

[VHDL-FPGA-Verilog] eda

Description: 该系统利用VHDL语言、PLD设计出租车计费系统，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了程序仿真。使其实现计费以及预置和模拟汽车启动、停止、暂停等功能，并动态扫描显示车费数目。-The system uses VHDL language, PLD design taxi billing system to MAX+ PLUS Ⅱ software as a development platform, the taxi meter system was designed and conducted a program simulation program. To achieve automotive billing and pre-and simulation start, stop, pause function, and dynamic scan showed the number of fare.
Platform: | Size: 164864 | Author: OFDM | Hits:
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