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Description: SOPC是Altera公司提出的一种灵活、高效的片上系统设计方案,它可以有选择地将处理器、存储器、I/O等系统设计需要的组件集成到一个PLD器件上。在SOPC设计中可方便地加入用户自定义逻辑。该文简要介绍了SOPC设计架构,然后通过一个实例,详细介绍了嵌入式系统中SOPC设计的实现方法和效果。-Altera Corporation SOPC is a flexible and efficient system-on-chip design, it can choose to have the processor, memory, I/O system design needs, such as components integrated into a PLD device. In SOPC design can be easily adding user-defined logic. The article briefly introduce the SOPC design framework, and then through an example of detailed SOPC embedded system design methods and results.
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Size: 173056 |
Author: 郑宏超 |
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Description: 可编程逻辑器件PLD入门教材很好的介绍了 该语言的运用以及设计-Programmable logic device PLD textbook good entry introduced the use of languages as well as design
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Size: 295936 |
Author: xulina |
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Description: 4*4键盘显示的4x4键盘识别与显示模块。小键盘中有0~f共16个按键，小键盘和数码管都连接到PLD芯片上，要求：按下哪个按键，数码管就显示哪个数码，松手后仍然显示该数码，直到按动新的按键。显示字符字形如表5-1所示。在此设计中，7段数码管只是个验证工具，因为实际应用中通常是一排数码管，而不是一个数码管。PLD芯片在此主要完成按键识别和显示驱动。-4* 4 keyboard shown 4x4 keyboard identification and display module. Small keyboard in the 0 ~ f has a total of 16 keys, small keyboard and digital tube are connected to the PLD chip, the requirements: Press any button, digital controls, it shows what the digital, let go after the remains showed that the digital, pressed until the new button. Show the shape of characters such as shown in Table 5-1. In this design, 7 digital tube is only a validation tool, for practical applications is usually a row of digital tube, rather than a digital pipe. PLD chips in the completion of this major keys to identify and display driver.
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Size: 88064 |
Author: hdd |
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Description: 四个拨码开关，拨上去对应的前四个LED灯亮，体现了pld io功能的灵活。请把拨码开关右上方的跳线帽跳上，同时拔掉ADC0804的跳线帽。-Four DIP switches, dial up the corresponding first four LED lights, reflect the function of flexible pld io. Please dial code switch at the top right of the jumper cap jumped, and pulled out the jumper cap ADC0804.
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Size: 64512 |
Author: liupeinan |
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Description: 现象为蜂鸣器频率的鸣响四个拨码开关，拨上去对应的前四个LED灯亮，体现了pld io功能的灵活。请把拨码开关右上方的跳线帽跳上，同时拔掉ADC0804的跳线帽。-Phenomenon for the buzzer frequency ringing four DIP switches, dial up the corresponding first four LED lights, reflect the function of flexible pld io. Please dial code switch at the top right of the jumper cap jumped, and pulled out the jumper cap ADC0804.
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Size: 183296 |
Author: liupeinan |
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Description: 高级FPGA教学实验指导书－逻辑设计部分.pdf
QuatusII5.0 是Altera 公司的最新产品。MaxplusII 是一套非常成功的PLD 开发软件，
虽然QuartusII 已经推出了4 年，并且Altera 宣布不再对MaxplusII 进行升级，但至今仍
有非常多的工程师在使用MaxplusII。 Altera 在QuartusII 中允许将软件界面设置为
MaxplusII 风格，以吸引MaxplusII 的用户转向QuartusII。安装QuartusII 时，软件会自
动询问，你准备使用何种界面：QuartusII 还是Maxplus-Senior FPGA experimental teaching guide book- part of logic design. PdfQuatusII5.0 are Altera
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Size: 1091584 |
Author: 董军 |
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Description: 16v8的测试程序，用abel4编辑器编辑。可以直接烧录在芯片中使用。-16v8 test procedures, using abel4 editor. Can be directly used in the chip burner.
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Size: 1024 |
Author: chengli |
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Description: 10分钟学会PLD设计!~
将带领大家完成你的第一个PLD设计，即使你从没有接触过PLD，也可以让你可以在十分种之内初步学会PLD设计！ 不信？ 呵呵 我们慢慢往下看。-PLD Design Institute 10 minutes! ~ Will take you to complete your first PLD design, even if you never come into contact with PLD, but also allows you can in a very preliminary kinds of PLD Design Institute! Do not believe? Ha ha we look down slowly.
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Size: 1417216 |
Author: lixstar |
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Description: 利用QuartusII的"MegaWizard Plug-In Manager",
设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE
把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行
时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。
2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER，
设计一个20bit的up_only COUNTER,
要求该COUNTER在FE0FA和FFFFF之间自动循环计数；
分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、
EPF10K70RC240-4几种芯片中的最大工作频率；
请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来
（仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
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Size: 31744 |
Author: 李侠 |
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Description: “数字电子技术”课程是电力类、自动化类和计算
机类等专业的一门重要的技术基础课,具有很强的实
践性,因此实验是“数字电子技术”课程教学中不可缺
少的重要环节。随着科学技术的发展,尤其是微电子
技术和计算机技术取得的重大进展,数字逻辑器件已
由中、小规模的TTL 集成电路发展到大规模和超大规
模的可编程逻辑器件( PLD) 。相对应地,数字逻辑电
路的研究和实现方法随之发生变化,从而促使“数字电
子技术”实验的实验内容、教学方式、实验手段和考核
方式也应该进行不断的更新、完善和开拓。相比之下,
传统的实验教学模式就显得格格不入,已不能适应现
代电子技术发展的需求,因此对电子技术实验教学模
式的改革就势在必行[1 ] 。-err
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Size: 154624 |
Author: 黄武彪 |
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Description: 纯组合逻辑构成的乘法器虽然工作速度比较快，但过于占用硬件资源，难以实现宽位乘法器，基于PLD器件外接ROM九九表的乘法器则无法构成单片系统，也不实用。这里介绍由八位加法器构成的以时序逻辑方式设计的八位乘法器，具有一定的实用价值，而且由FPGA构成实验系统后，可以很容易的用ASIC大型集成芯片来完成，性价比高，可操作性强。-err
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Size: 1024 |
Author: makai |
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Description: PLD内部锁相环,解决方案,方法介绍,设计思想.-PLD internal phase-locked loop, solutions, methods, the design idea.
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Size: 69632 |
Author: 张大明 |
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Description: GAL16v8编程，cupl语言说明，GAL硬件结构和原理-GAL16v8 programming, cupl language, GAL hardware structure and principle
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Size: 6462464 |
Author: 徐太刚 |
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Description: 在一个32单元CPLD中实现的I2C SLave device-Minimal I2C Slave Device in a 32cell PLD
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Size: 1432576 |
Author: ttt |
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Description: 在深圳固高科技器械平台上实现倒立摆的实验研究以及 相关器械使用手册，能实现倒立摆的PLD调节等等！-In Shenzhen high-tech equipment solid platform implementation of the experimental study of the inverted pendulum as well as related equipment manuals can achieve inverted pendulum PLD regulation and so on!
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Size: 1745920 |
Author: 刘鑫 |
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Description: modesim使用简介，包含PLD设计流程和相关内容。-About modesim use, including PLD design process and related content.
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Size: 505856 |
Author: yaya |
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Description: -- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
--- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
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Size: 4096 |
Author: djs |
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Description: -- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn--- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
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Size: 4096 |
Author: djs |
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Description: 1，其语法适用于各种PLD 器件；2，语言本身高度结构化；3，逻辑描述的形式灵活多
样；4，具有仿真和测试用的测试向量；5，允许使用高效的宏定义及指令。-1, the syntax applicable to a variety of PLD devices 2, highly structured language itself 3, the logic described in the form of flexible and diverse 4, with simulation and testing of test vectors 5, allowing the use of efficient macro definitions and instructions.
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Size: 30956544 |
Author: 何新 |
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Description: 伴随高速DSP技术的广泛应用，实时快速可靠地进行数字信号处理成为用户追求的目标。同时，由于可编程器件在速度和集成度方面的飞速提高，使得利用硬件实现数字信号实时快速可靠处理有了新的途径。-With the wide applications of high-speed DSP technology, the user pursuit the target that it is real-time、high-speed and reliable to process digital signal. At the same time, the PLD has been improved in the aspect of speed and integration, which makes a new approach to achieve real-time、high-speed and reliable digital signal processing with hardware.
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Size: 102400 |
Author: yanbo |
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