Search - PLD - CodeBus

[Books] PLD实验参考源程序.rar

Description:
Platform: | Size: 14842 | Author: | Hits:

Description: 增加ASCII.C的一个ASCI码(7F),用于虚拟按键用修改UART串口的命令解析程序，修改RTC的pcf8563中断部分。精简IIC和smart_timer代码,添加define.h的宏定义。修改system.c里的消息堆栈的宏定义增加ii.c函数,支持对eeprom的打包增加由PLD或者GPIO输出的模拟UART，在6个CLOCK下速度为57.6K 增加消息的优先级功能，消息类型的前4位为消息的优先级，后4位为消息的类型试用于初学单片机并且想更上一层楼的，或者有些基础，想减少工作量的。-an increase ASCII.C the ASCI code (7F) for the virtual keys with serial UART to amend the order analytic procedures, the revised RTC pcf8563 interruption part. IIC and smart_timer streamline code, add the definition of Acer define.h. The revised system.c news stack macros increase II.c function, support for EEPROM packaged increase from the PLD or GPIO output analog UART, in the next six CLOCK speed of 57.6K news of the priority function of the type of information before news of the four priority levels after four types of information on the trial beginner to a higher level and SCM, or some foundation, we want to reduce the workload.
Platform: | Size: 2233228 | Author: 初学者 | Hits:

[Other resource] cpld_bus

Description: CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
Platform: | Size: 218582 | Author: hamlemon | Hits:

[Other resource] 《Verilog黄金指南》中文翻译版

Description: Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法-Verilog learning materials, they simply PLD development language, and to highlight the key Verilog syntax
Platform: | Size: 469160 | Author: 张 | Hits:

[Com Port] fa

Description: PLD串口实验通信程序,可以实现实验板和PC机之间的数据传送,并显示在LED上-PLD serial communications experimental procedure can be achieved experimental board and the PC data transmission, and the LED display on
Platform: | Size: 436462 | Author: 谭茂 | Hits:

[Develop Tools] fpga时钟设计

Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将导致错误的行为，并且调试困难、花销很大。在设计PLD/FPGA时通常采用几种时钟类型。时钟可分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD / FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
Platform: | Size: 402195 | Author: 与言 | Hits:

[Develop Tools] fpga 和 cpld入门教程

Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA / CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: | Size: 4329224 | Author: 小易 | Hits:

[Driver Develop] Q7230

Description: PLD-N分频程序，使用时可以任意修改（VHDL）-PLD --N procedures can be arbitrary use of Laws (VHDL)
Platform: | Size: 190874 | Author: C51 | Hits:

[Other resource] 44vhdl

Description: 44个vhdl实例注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44575 | Author: 土木文田 | Hits:

[Embeded-SCM Develop] PLDprogrammingnote

Description: PLD编程笔记使用abel语言的有关个人心得笔记-PLD programming language abel use of the personal experiences Notes
Platform: | Size: 157803 | Author: fsdf | Hits:

[matlab] pld

Description: this book about pld discrub
Platform: | Size: 7264256 | Author: raad | Hits:

[VHDL-FPGA-Verilog] PLD

Description: PLD编程手册，gal 介绍GAL系列芯片编程方法-PLD programming manual, gal GAL series chip programming method introduced
Platform: | Size: 157696 | Author: 黑色羊毛衫 | Hits:

[VHDL-FPGA-Verilog] PLD

Description: PLD实验代码，包括格雷码计数器、键盘扫描和LED点阵显示、SRAM读写、LCD12864显示汉字。-PLD experimental code, including the Gray code counter, keyboard scanning and LED dot matrix display, SRAM read and write, LCD12864 display Chinese characters.
Platform: | Size: 132096 | Author: 马昭鑫 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Books] PLD实验参考源程序.rar

[Other resource] 实用单片机系统

[Other resource] cpld_bus

[Other resource] 《Verilog黄金指南》中文翻译版

[Com Port] fa

[Develop Tools] fpga时钟设计

[Develop Tools] fpga 和 cpld入门教程

[Driver Develop] Q7230

[Other resource] 44vhdl

[Embeded-SCM Develop] PLDprogrammingnote

[matlab] pld

[VHDL-FPGA-Verilog] PLD

[VHDL-FPGA-Verilog] PLD

[VHDL-FPGA-Verilog] PLD

[VHDL-FPGA-Verilog] Pld-based-VGA-display

[VHDL-FPGA-Verilog] pld-tutorial

[Other] Pld-Programming-Using-Vhdl

[Program doc] Initial-code-of-PLD

[Picture Viewer] PLD

[Other] AMD_PLD Design Methodology

CodeBus www.codebus.net