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Platform: |
Size: 3072 |
Author: math |
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Description: smdk2410 cpld code
s3c2410 demo board cpld code -smdk2410 cpld codes3c2410 demo board cpld code
Platform: |
Size: 78848 |
Author: 士大夫 |
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Description: 可以直接生产的s3c2410pcb和原理图-Can be directly produced s3c2410pcb and schematic diagram
Platform: |
Size: 2433024 |
Author: 周杨军 |
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Description: 用WINCE进行嵌入式开发的源代码开发板S3C2410-WINCE embedded with the development of source code S3C2410 development board
Platform: |
Size: 33792 |
Author: cindy |
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Description: 单片机用总线方式与CPLD系统进行通信。-Single-chip mode with the bus system to communicate with the CPLD.
Platform: |
Size: 1024 |
Author: wql |
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Description: 基于PLD的RS码编译码器设计，用VHDL语言编写，编译通过，测试结果正确。-PLD-based encoding and decoding of RS code design, using VHDL language, the compiler is passed, the test results correctly.
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Size: 15360 |
Author: li.j |
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Description: 基于BP神经网络整定的PlD控制，神经网络，根据系统的运行状态，调节PID控制器的参数，以期达到某种性能指标
的最优化，使输出层神经元的输出状态对于控制器的三个可调参数-BP neural network based on the PLD-tuning control, neural network, in accordance with the system running, adjusting the parameters of PID controller with a view to attaining certain performance metrics are optimized so that the output layer neuron output state for the three controllers can be tune parameters
Platform: |
Size: 1024 |
Author: feiyang |
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Description: 用于编可编辑芯片用,如gal16v18芯片等,有几个文件, 内有说明等!-Series can be used to edit the chips used, such as chips gal16v18, there are several documents, there are descriptions!
Platform: |
Size: 35840 |
Author: mabaohua |
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Description: 4乘4键盘识别与显示程序和说明（vhdl）
设计了一个的4x4键盘识别与显示模块。小键盘中有0~f共16个按键，小键盘和数码管都连接到PLD芯片上。-4 x 4 keyboard and display identification and description of procedures (vhdl) designed a recognition of the 4x4 keypad and display module. Small keyboard in the 0 ~ f total of 16 keys, small keyboard and digital tube are connected to the PLD chip.
Platform: |
Size: 88064 |
Author: coolrainy |
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Description: 基于复杂可编程逻辑器件(CPLD)的120MHz高速A_D采集卡的设计-Based on complex programmable logic device (CPLD) of 120MHz high-speed acquisition card A_D Design
Platform: |
Size: 66560 |
Author: alpha |
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Description: 从FPGA或PLD转换到门阵是经济高效的，有时甚至只需几百个单元就能实现。这已经引起越来越多设计者提出同样的问题：这种转换设计需要什么后续技术？事实上转换-From the FPGA or PLD Gate Array conversion to an economic and efficient, sometimes even just a few hundred units will be able to achieve. This has aroused more and more designers to raise the same question: what is required of such conversion design follow-up technology? In fact the conversion
Platform: |
Size: 73728 |
Author: |
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Description: PLD驱动内核，给与了具体原理图的说明和构建，很有参考意义！-PLD-driven kernel, to give a specific description of schematic and construction, is very useful!
Platform: |
Size: 39936 |
Author: yeqiang |
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Description: 电子锁的vhdl实现
（pld数字系统设计上）-VHDL realization of the electronic lock (pld digital system design)
Platform: |
Size: 1024 |
Author: 阿乔 |
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Description: 51加cpld测试程序
51加cpld测试程序-51 plus 51 plus test procedure CPLD CPLD test procedures
Platform: |
Size: 66560 |
Author: zhangren |
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Description: PLD设计
Maxplus使用
quartusII中文教程-PLD Design Maxplus use Chinese quartusII Guide
Platform: |
Size: 4997120 |
Author: haoxin |
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Description: 注1： 含有不可综合语句，请自行修改
注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意
注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
-Note 1: contains a comprehensive statement can not, please amend Note 2: Some PLD only permit I/O port of external tri-state, does not support internal tri-state, the use of when we should pay attention Note 3: the design of RAM
Platform: |
Size: 44032 |
Author: 朱明 |
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Description: 用来实现VGA发生时序，显示颜色，用CPLD实现-Used to realize the occurrence VGA timing, display color, with CPLD realize
Platform: |
Size: 312320 |
Author: |
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Description: PLD设计的定时抢答器报告，有电路原理图，做硬件的朋友可以看看，EPROM7128S的-Answer PLD timing device design report, there are circuit schematics, so a friend can look at hardware, EPROM7128S the
Platform: |
Size: 487424 |
Author: 麦佳 |
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Description: 用fpga实现的DA转换器，有说明和源码，VDHL文件。
A PLD Based Delta-Sigma DAC
Delta-Sigma modulation is the simple, yet powerful,
technique responsible for the extraordinary
performance and low cost of today s audio CD
players. The simplest Delta-Sigma DAC consists of a
Delta-Sigma modulator and a one bit DAC. Since,
both of these components can be realized using
digital circuits, it is possible to implement a low
precision Delta-Sigma DAC using a PLD.-Using FPGA to achieve the DA converter, has descriptions and source code, VDHL document. A PLD Based Delta-Sigma DACDelta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinaryperformance and low cost of today s audio CDplayers. The simplest Delta-Sigma DAC consists of aDelta-Sigma modulator and a one bit DAC. Since , both of these components can be realized usingdigital circuits, it is possible to implement a lowprecision Delta-Sigma DAC using a PLD.
Platform: |
Size: 58368 |
Author: 开心 |
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Description: 该PDF文档是CPLD/FPGA的入门教程。里面叙述了PLD的基本结构，选择CPLD/FPGA的方式方法。-The PDF document is the CPLD/FPGA introductory tutorial. Which describes the basic structure of PLD, select the CPLD/FPGA ways.
Platform: |
Size: 192512 |
Author: 李鑫旺 |
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