Search - PLD - CodeBus

[Com Port] fa

Description: PLD串口实验通信程序,可以实现实验板和PC机之间的数据传送,并显示在LED上-PLD serial communications experimental procedure can be achieved experimental board and the PC data transmission, and the LED display on
Platform: | Size: 436224 | Author: 谭茂 | Hits:

[Books] fpga 和 cpld入门教程

Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA/CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: | Size: 4328448 | Author: 小易 | Hits:

[Driver Develop] Q7230

Description: PLD-N分频程序，使用时可以任意修改（VHDL）-PLD--N procedures can be arbitrary use of Laws (VHDL)
Platform: | Size: 190464 | Author: C51 | Hits:

[VHDL-FPGA-Verilog] 44vhdl

Description: 44个vhdl实例注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[Embeded-SCM Develop] PLDadd

Description: 关于pld编程笔记的进一步补充。对前文错误有些纠正，同时补充了一些新的例程 -Programming Notes on pld further added. Right before the text to correct some mistakes, adding a number of new routines
Platform: | Size: 103424 | Author: fsdf | Hits:

[VHDL-FPGA-Verilog] CPLD_CODE1

Description: ju继续上载CPLD的黄金参考源代码，希望对电子爱好者有所帮助-ju continue on the CPLD gold reference source, and I hope to help e-lovers
Platform: | Size: 9216 | Author: 求知 | Hits:

[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] decode_for_m68008

Description: -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] mo0re_FSM

Description: -- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] FSM02

Description: 异步复位状态机 -- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn -asynchronous reset state machine-- State Machine with Asynchronou 's Reset-- dowload from : www.fpga.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] BoothMultiplier

Description: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
Platform: | Size: 2048 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] wave_gen

Description: 波形发生器，带TESTBENCH，多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] dds-design

Description: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Platform: | Size: 1024 | Author: 魏杰 | Hits:

[VHDL-FPGA-Verilog] DSPuva16

Description: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Platform: | Size: 15360 | Author: 魏杰 | Hits:

[VHDL-FPGA-Verilog] PCB(Cadence)

Description: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Platform: | Size: 467968 | Author: 魏杰 | Hits:

[Software Engineering] PLDcPLDFPGA

Description: PLD、CPLD、FPGA有何不同？（问与答）-PLD, CPLD, FPGA any different? (Answer)
Platform: | Size: 14336 | Author: 薛岩峰 | Hits:

[SCM] upsd3200_eeprom

Description: TI公司的增强型8位单片机upsd32xx系列芯片，利用片上flash模拟EEPROM使用，方便保存参数，无需外接参数保存芯片了。内含英文说明文档和keil c源码，PLD项目源码。-TI's enhanced SCM upsd32xx 8 series chips, the use of on-chip flash EEPROM use of simulation to facilitate the preservation parameters, external parameters need to preserve the chip. Documents containing English and keil c source, PLD source projects.
Platform: | Size: 261120 | Author: 黄国芬 | Hits:

[SCM] upsd33xx_Sound_example

Description: 增强型单片机UPSD33XX系列芯片做音频发生器例程。内含KEIL源码和PLD源码。-enhanced chip microcontroller series UPSD33XX done Audio Generator routines. Intron KEIL source and PLD source.
Platform: | Size: 1857536 | Author: 黄国芬 | Hits:

[Embeded-SCM Develop] 51board

Description: MCU51_CPLD开发板电路图。在整个200M的开发资料中感觉这副电路图纸最重要，推荐大家。-MCU51_CPLD Development Board circuit. 200 M in the development of information feeling this pair of the most important circuit drawings, we recommend.
Platform: | Size: 165888 | Author: wei | Hits:

[SCM] UsbBlaster

Description: 直接应用USB接口，对FPGA/CPLD等芯片的下载。便于用手提电脑的玩家使用。大家可以里面有单片机的源程序和PLD的下载程序。-Direct application of USB interface on the FPGA/CPLD chip, such as downloads. Easy to use laptop computers to use the player. Everyone can have MCU inside and PLD source of the download process.
Platform: | Size: 21504 | Author: feng | Hits:

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