Search - PLD - CodeBus

[SCM] 实用单片机系统

Description: 增加ASCII.C的一个ASCI码(7F),用于虚拟按键用修改UART串口的命令解析程序，修改RTC的pcf8563中断部分。精简IIC和smart_timer代码,添加define.h的宏定义。修改system.c里的消息堆栈的宏定义增加ii.c函数,支持对eeprom的打包增加由PLD或者GPIO输出的模拟UART，在6个CLOCK下速度为57.6K 增加消息的优先级功能，消息类型的前4位为消息的优先级，后4位为消息的类型试用于初学单片机并且想更上一层楼的，或者有些基础，想减少工作量的。-an increase ASCII.C the ASCI code (7F) for the virtual keys with serial UART to amend the order analytic procedures, the revised RTC pcf8563 interruption part. IIC and smart_timer streamline code, add the definition of Acer define.h. The revised system.c news stack macros increase II.c function, support for EEPROM packaged increase from the PLD or GPIO output analog UART, in the next six CLOCK speed of 57.6K news of the priority function of the type of information before news of the four priority levels after four types of information on the trial beginner to a higher level and SCM, or some foundation, we want to reduce the workload.
Platform: | Size: 2233344 | Author: 初学者 | Hits:

[Other] 《Verilog黄金指南》中文翻译版

Description: Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法-Verilog learning materials, they simply PLD development language, and to highlight the key Verilog syntax
Platform: | Size: 468992 | Author: 张 | Hits:

[Books] fpga时钟设计

Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将导致错误的行为，并且调试困难、花销很大。在设计PLD/FPGA时通常采用几种时钟类型。时钟可分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
Platform: | Size: 402432 | Author: 与言 | Hits:

[Embeded-SCM Develop] PLDprogrammingnote

Description: PLD编程笔记使用abel语言的有关个人心得笔记-PLD programming language abel use of the personal experiences Notes
Platform: | Size: 157696 | Author: fsdf | Hits:

[Embeded-SCM Develop] PLDprogram

Description: PLD可编程器件教学实验系统用户使用指南zhege 是我们自己翻译的一个指南，大家可以-PLD teaching experimental system user guide zhege is our own translation of a mean South, we can see!
Platform: | Size: 52224 | Author: 胡茂海 | Hits:

[Other] xapp349

Description: PLD与8051接口的参考设计-PLD interface with the 8051 reference design
Platform: | Size: 31744 | Author: shang808 | Hits:

[VHDL-FPGA-Verilog] led

Description: vhdl实现“PLD电子技术”（文字显示）-VHDL achieve PLD electronic technology (text)
Platform: | Size: 1024 | Author: 阿乔 | Hits:

[Software Engineering] pld

Description: 十分钟学会pld开发的流程，资料比较简单希望你们能够喜欢-Institute of PLD 10 minutes developed flow, the data is relatively simple I hope you can like
Platform: | Size: 757760 | Author: zhangxi | Hits:

[Other Embeded program] fm

Description: 编辑软件，pld文件的编辑，主要用于gal16v8的汇编。-Editing software, pld document editing, mainly used in the compilation of gal16v8.
Platform: | Size: 319488 | Author: 周工 | Hits:

[Other] VerilogHDL

Description: 课程设计，使用硬件描述语言对数字电路与系统进行建模，仿真与实现的方法，ASM图，PLD器件-Curriculum design, the use of hardware description language for digital circuits and systems modeling, simulation and realization of the method, ASM chart, PLD device
Platform: | Size: 2572288 | Author: hexiang | Hits:

[VHDL-FPGA-Verilog] PLD_SRAM

Description: PLD自增读写SRAM,有好的参照作用，希望大家指点和帮助。-PLD by reading and writing since the SRAM, has reference to the role of good, I hope everyone pointing and help.
Platform: | Size: 20480 | Author: 王明 | Hits:

[VHDL-FPGA-Verilog] pld

Description: 四字路口交通灯管理器的设计（含波形输出）-Management of traffic lights at the junction word design (including waveform output)
Platform: | Size: 109568 | Author: 庞永亮 | Hits:

[Other] FPGA_CPLDDDDD

Description: 可编程逻辑器件 pld/fpga,vhdl/verilog的相关学习资料，设计技巧-Programmable logic device pld/fpga, vhdl/verilog relevant learning materials, design techniques
Platform: | Size: 5028864 | Author: www | Hits:

[VHDL-FPGA-Verilog] ttt

Description: 该系统利用VHDL语言、PLD设计出租车计费系统，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了程序仿真。使其实现计费以及预置和模拟汽车启动、停止、暂停等功能，并动态扫描显示车费数目。-The system is the use of VHDL language, PLD design taxi billing system to MAX+ PLUS Ⅱ software as a development platform designed billing system procedures taxi and carried out a simulation program. To the achievement of pre-billing and simulation, as well as car to start, stop, pause and other functions, and dynamic scan shows the number of fares.
Platform: | Size: 183296 | Author: cch | Hits:

[VHDL-FPGA-Verilog] PLD(3.8M)

Description: VHDL入门学习资料，介绍详细适合初学大量PPT文档-VHDL Introduction to learning information about the details of a large number of PPT files for beginners
Platform: | Size: 4884480 | Author: 简单 | Hits:

[Other] PLD-Design-Institut-for-10-minutes

Description: 10分钟学会PLD设计，分别采用VHDL、Verilog-HDL和原理图输入方式设计实验，并下载到PLD实验板进行实际运行。-PLD Design Institute for 10 minutes, respectively, the use of VHDL, Verilog-HDL and schematic design of the experimental input, and downloaded to the PLD to the actual operation of the experimental plate.
Platform: | Size: 870400 | Author: 宋大力 | Hits:

[Windows Develop] PLD-design-skills

Description: PLD设计技巧，包括多种系统和电路应用设计，PDF和PPT两种格式。-PLD design skills, including a variety of system and circuit design applications, PDF and PPT formats.
Platform: | Size: 1781760 | Author: 宋大力 | Hits:

[Software Engineering] abel

Description: ABEL PLD 可编程逻辑元件参考语法-ABEL PLD
Platform: | Size: 157696 | Author: axin | Hits:

[Software Engineering] AlteraArticleContestPapers

Description: 本源码为Altera中国大学生电子设计文章竞赛的历届获奖论文汇编，内容主题涵盖如下4个方面： PLD在通讯、消费类、计算机和工业控制方面的应用 Altera器件、Quartus® II 软件的设计和优化技术 Altera FPGA在数字信号处理中的应用 Nios® II 软处理器在各领域的应用获奖作品均是是参赛者独立设计的未曾公开发表过的原创性作品，在作品原创性和特色性、实用性（结合当前的热点应用）和作品的完整性（有明确的实验或仿真数）上均有很多优势。每年的获奖论文共18篇左右。-The source code for Altera Chinese Undergraduate Electronic Design Contest of the previous article, the compilation of award-winning paper, which covers four aspects as follows: PLD in the communications, consumer, computer and industrial control applications Altera devices, Quartus ® II software for design and optimization Altera FPGA technology in digital signal processing applications in the Nios ® II soft processor applications in various fields is the award-winning works were designed by participants independence had not been published original works in the works and the characteristics of originality, practical and (combined with the application of the current hot spots) and the integrity of the work (there are clearly a number of experimental or simulation) have many advantages on. The annual award-winning total of 18 papers around.
Platform: | Size: 26785792 | Author: 成逛 | Hits:

[VHDL-FPGA-Verilog] PLD

Description: vhdl语言实现cpld功能，本程序包括全加器，触发器，交通灯程序，适用maxII软件调试。-include full_adder,plus,traffic
Platform: | Size: 673792 | Author: yvonna | Hits:

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