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[VHDL-FPGA-Verilog] DDS

Description: A simple VHDL implementation of a DDS on Xilinx Spartan 3E Starter Kit development board
Platform: | Size: 107520 | Author: Iepu | Hits:

Description: DDS信号发生器，利用VHDL实现，可根据频率控制字的改变输出不同频率的信号，最高可到达10MBPS-DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
Platform: | Size: 784384 | Author: 陈宇 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器，累加器，波形存储器-In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
Platform: | Size: 351232 | Author: ice | Hits:

[VHDL-FPGA-Verilog] DDS-top

Description: 能够基于DDS实现输出正弦波形的一部分程序，利用Verilog HDL语言编写。-Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
Platform: | Size: 299008 | Author: evil | Hits:

[VHDL-FPGA-Verilog] dds

Description: fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
Platform: | Size: 571392 | Author: wangjian | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA实现直接数字频率合成（DDS），使用EP1C3T144C8通过调试-Cyclone,aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Platform: | Size: 140288 | Author: qiuwang | Hits:

[SCM] dds

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
Platform: | Size: 28672 | Author: nbonwenli | Hits:

[Books] DDS

Description: DDS设计指南，包括DDS的解构，计算公式与频谱分析，是学习DDS原理的好资料-DDS design guidelines, including the deconstruction DDS, calculation formula and spectral analysis, is the principle of learning good information DDS
Platform: | Size: 584704 | Author: 刘建斌 | Hits:

[matlab] DDS

Description: 基于dds的函数发生器和基于matlab的扫雷游戏-Dds-based function generator and the mine-based game matlab
Platform: | Size: 2319360 | Author: 雄鹰 | Hits:

[Graph Drawing] dds(heli)

Description: DDS用verilog 实现，可以实现方波、正弦和三角-DDS using verilog realized, can be square wave, sinusoidal and triangular
Platform: | Size: 428032 | Author: qian | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用DE2开发板做的DDS程序，频率分辨率可以达到1Hz！-DE2 development board to do with the DDS process, the frequency resolution can be achieved 1Hz!
Platform: | Size: 1059840 | Author: liukai | Hits:

[SCM] DDS

Description: dds 正弦信号发生器步进100HZ 最高频率可达900kHZ 最低频率可大2.3Khz-dds signal generator sin walingbeam 100HZ
Platform: | Size: 989184 | Author: lin65505578 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于DDS原理的几种信号发生器的设计的几篇论文，使用FPGA平台或者FPGA和PC共同平台实现-DDS-based signal generator several principles of design, the use of FPGA or FPGA platform and a common platform PC
Platform: | Size: 591872 | Author: 王霄洲 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 如何利用FPGA产生DDS调频信号很具体的-How to make use of DDS generated FM signal FPGA specific
Platform: | Size: 756736 | Author: 梁梁 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Platform: | Size: 117760 | Author: tiancheng | Hits:

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[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS-top

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[SCM] dds

[Books] DDS

[matlab] DDS

[Graph Drawing] dds(heli)

[VHDL-FPGA-Verilog] DDS

[SCM] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[Program doc] FPGA-DDS-FM

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

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