Description: Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [mif] - use metlab production sine wave and tria
- [MIF_create] - MIF file generator quartus II software f
- [sine] - chdl 64 bit counter, using sine wave gen
- [DDS] - The use of EDA technology and FPGA devel
- [SPWM] - VHDL using written natural sampling SPWM
- [signal] - written in verilog serial control signal
- [FPGArealiztionofdigitalsignalprocessing] - Digital Signal Processing FPGA realizati
- [vgav2] - fpga 640*480 60HZ vga output，writed in v
- [dds_quicklogic] - dds verilog source code makes sense
File list (Check if you may need any files):
DDS
...\1024.mif
...\512.mif
...\clock_d2.bsf
...\clock_d2.v
...\cmp_state.ini
...\control.bsf
...\control.v
...\control.v.bak
...\creat.c
...\creat.exe
...\datachoose.bsf
...\datachoose.v
...\db
...\..\altsyncram_88s.tdf
...\..\DDSFPGA.db_info
...\..\DDSFPGA.eco.cdb
...\..\DDSFPGA.sld_design_entry.sci
...\..\DDSFPGA_cmp.qrpt
...\..\DDSFPGA_sim.qrpt
...\DDSFPGA.asm.rpt
...\DDSFPGA.bdf
...\DDSFPGA.done
...\DDSFPGA.fit.eqn
...\DDSFPGA.fit.rpt
...\DDSFPGA.fit.summary
...\DDSFPGA.flow.rpt
...\DDSFPGA.map.eqn
...\DDSFPGA.map.rpt
...\DDSFPGA.map.summary
...\DDSFPGA.pin
...\DDSFPGA.pof
...\DDSFPGA.qpf
...\DDSFPGA.qsf
...\DDSFPGA.qws
...\DDSFPGA.sim.rpt
...\DDSFPGA.sof
...\DDSFPGA.tan.rpt
...\DDSFPGA.tan.summary
...\DDSFPGA.vwf
...\DDSFPGA_assignment_defaults.qdf
...\Key.bsf
...\key.v
...\romlookup.bsf
...\romlookup.v
...\romlookup_bb.v
...\squwave.bsf
...\squwave.v
...\squwave.v.bak
...\triawave.bsf
...\triawave.v
...\triawave.v.bak
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