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[VHDL-FPGA-Verilog] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Platform: | Size: 1378304 | Author: 谭儆轩 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Platform: | Size: 468992 | Author: qlg | Hits:

Description: 实现dds功能，利用quartus软件，子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.
Platform: | Size: 2854912 | Author: lijingfeng | Hits:

[SCM] DDS

Description: 所以与DDS有关的中文资料及调试心得，打包下载-So with the DDS-related information and debug the Chinese experience, packing Download
Platform: | Size: 9991168 | Author: 仙儿 | Hits:

[VHDL-FPGA-Verilog] vhdl-dds

Description: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Platform: | Size: 88064 | Author: martin | Hits:

[matlab] dds

Description: 用MATLAB观察DDS输出波形 -Using MATLAB to observe DDS output waveform using MATLAB observation DDS output waveform
Platform: | Size: 3072 | Author: wangzhaohui | Hits:

[SCM] DDS

Description: 用8051控制DDS信号发生器，产生1HZ-10MHz的正弦波/三角波/方波-DDS with 8051 control signal generator, producing the 1HZ-10MHz sine/triangle/square wave
Platform: | Size: 43008 | Author: 徐小平 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
Platform: | Size: 53248 | Author: 李达兴 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,
Platform: | Size: 2096128 | Author: lqb | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[SCM] dds

Description: dds 信号发生器的参考程序，，精工参考-dds reference signal generator procedures, Seiko reference
Platform: | Size: 1024 | Author: niuxq | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS原理介绍，里面是有时序图和系统设计！-DDS principle that there is a timing diagram and system design!
Platform: | Size: 454656 | Author: dragon | Hits:

[OS Develop] dds

Description: 这是一个用vhdl语言实现dds的例子，已在quartusII里调通并可以下载到实验箱上，功能正确-This is a use of VHDL language dds example, has been in tune quartusII pass and can be downloaded to the experimental box, the function correctly
Platform: | Size: 331776 | Author: leezhihui | Hits:

[SCM] dds

Description: 基于ATMEGA16和DDS的信号发生器的代码，内含一个基于IAR集成开发环境的工程，可直接用IAR打开，编译并烧入单片机，是本人花了半个月的一个成果-ATmega16 and DDS-based signal generator code, contains a IAR integrated development environment based on the works, can be directly used IAR open, compile and burn into the single-chip, is I spent a half an outcome
Platform: | Size: 97280 | Author: 陈晓涛 | Hits:

[Other] DDS

Description: 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
Platform: | Size: 1682432 | Author: | Hits:

[SCM] DDS

Description: 《DDS 原理简介》，DDS即直接数字频率合成器原理简介及系统设计与实现- DDS Principle , DDS direct digital synthesizer Principle and System Design and Implementation
Platform: | Size: 454656 | Author: 范田田 | Hits:

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