Description: This is a use of VHDL language dds example, has been in tune quartusII pass and can be downloaded to the experimental box, the function correctly
- [pll] - Using FPGA digital phase-locked loop, de
- [dds] - The DDS-based FPGA design, the procedure
File list (Check if you may need any files):
dds
...\add.bsf
...\add.vhd
...\Block1.bdf
...\db
...\..\altsyncram_2s21.tdf
...\..\altsyncram_ipr.tdf
...\..\altsyncram_k331.tdf
...\..\altsyncram_t431.tdf
...\..\dds.asm.qmsg
...\..\dds.asm_labs.ddb
...\..\dds.cbx.xml
...\..\dds.cmp.cdb
...\..\dds.cmp.hdb
...\..\dds.cmp.kpt
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.cmp2.ddb
...\..\dds.dbp
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.eds_overflow
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.map.cdb
...\..\dds.map.hdb
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.rpp.qmsg
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgate.rvd
...\..\dds.sgate_sm.rvd
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.signalprobe.cdb
...\..\dds.sim.hdb
...\..\dds.sim.qmsg
...\..\dds.sim.rdb
...\..\dds.sim.vwf
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\..\wed.zsf
...\dds.asm.rpt
...\dds.bdf
...\dds.done
...\dds.dpf
...\dds.fit.eqn
...\dds.fit.rpt
...\dds.fit.smsg
...\dds.fit.summary
...\dds.flow.rpt
...\dds.map.eqn
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.pof
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sim.rpt
...\dds.sim.vwf
...\dds.sof
...\dds.tan.rpt
...\dds.tan.summary
...\dds.vwf
...\dds_assignment_defaults.qdf
...\rom01.bsf
...\rom01.cmp
...\rom01.mif
...\rom01.vhd
...\rom10.mif
...\Waveform1.vwf
Download