Description: The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
- [dds] - Direct Digital Frequency Synthesizer dds
- [altclklock] - Octave frequency-locking, VHDL program,
- [test] - VHDL realize many times frequency multip
- [firOK] - fir filter design, this filter Fs for 44
- [dds] - This is a use of VHDL language dds examp
- [PLL] - verilog PLL code, and the function of PL
- [DDS] - this is a code for DDS in Verilog
- [pll] - frequency multiple rely on dpll，unknown
- [DDS] - DDS-based signal generator several princ
- [dds] - How to make use of DDS generated FM sign
File list (Check if you may need any files):
ep2c35_4_17_dds
...............\dds.asm.rpt
...............\dds.cdf
...............\dds.done
...............\dds.fit.rpt
...............\dds.fit.smsg
...............\dds.fit.summary
...............\dds.flow.rpt
...............\dds.map.rpt
...............\dds.map.summary
...............\dds.pin
...............\dds.pof
...............\dds.qpf
...............\dds.qsf
...............\dds.qws
...............\dds.sof
...............\dds.tan.rpt
...............\dds.tan.summary
...............\dds.v
...............\dds.v.bak
...............\dds_rom.inc
...............\dds_rom.mif
...............\dds_rom.tdf
...............\dds_rom_waveforms.html
...............\dds_test.v
...............\dds_top.v
...............\dds_top.v.bak
...............\pll.inc
...............\pll.ppf
...............\pll.tdf
...............\pll_waveforms.html
...............\prev_cmp_dds.qmsg
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