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Title: Verilog Download
  • Category:
  • SCM
  • Tags:
  • [VHDL] [源码]
  • File Size:
  • 24.84kb
  • Update:
  • 2008-10-13
  • Downloads:
  • 0 Times
  • Uploaded by:
 Description: DDS, FPGA generated using Verilog language
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