Description: Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
- [VHDLElaborateson100cases.Rar] - VHDL Elaborates on 100 cases. Detailed a
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [DDS1] - DDS signal generator, can produce a vari
- [DDS] - FPGA with 51 and realize the process of
- [Verilog] - DDS, FPGA generated using Verilog langua
- [dds] - ewfreytrgrwf reggwrter rgterthhrgdfs rgd
- [DDS] - Quartus on the DDS, can occur sine wave,
- [DDS] - Verilog language technology based on the
- [dds] - verilog hardware language DDS, using the
- [sin_producer] - verilog sin signal producer
File list (Check if you may need any files):
dds\adapt.bsf
...\adapt.v
...\adapt.v.bak
...\altfp_add_sub0.bsf
...\altfp_add_sub0.cmp
...\altfp_add_sub0.inc
...\altfp_add_sub0.qip
...\altfp_add_sub0.v
...\altfp_add_sub0_bb.v
...\altfp_add_sub0_inst.v
...\db\add_sub_0ph.tdf
...\..\add_sub_qmj.tdf
...\..\altsyncram_b191.tdf
...\..\dds.asm.qmsg
...\..\dds.asm.rdb
...\..\dds.asm_labs.ddb
...\..\dds.cbx.xml
...\..\dds.cmp.bpm
...\..\dds.cmp.cbp
...\..\dds.cmp.cdb
...\..\dds.cmp.ecobp
...\..\dds.cmp.hdb
...\..\dds.cmp.kpt
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp_merge.kpt
...\..\dds.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
...\..\dds.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.lpc.html
...\..\dds.lpc.rdb
...\..\dds.lpc.txt
...\..\dds.map.bpm
...\..\dds.map.cbp
...\..\dds.map.cdb
...\..\dds.map.ecobp
...\..\dds.map.hdb
...\..\dds.map.kpt
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.map_bb.cdb
...\..\dds.map_bb.hdb
...\..\dds.map_bb.logdb
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.smart_action.txt
...\..\dds.sta.qmsg
...\..\dds.sta.rdb
...\..\dds.sta_cmp.6_slow_1200mv_85c.tdb
...\..\dds.syn_hier_info
...\..\dds.tiscmp.fast_1200mv_0c.ddb
...\..\dds.tiscmp.slow_1200mv_0c.ddb
...\..\dds.tiscmp.slow_1200mv_85c.ddb
...\..\dds.tis_db_list.ddb
...\..\dds.tmw_info
...\..\logic_util_heursitic.dat
...\..\pll_altpll.v
...\..\prev_cmp_dds.asm.qmsg
...\..\prev_cmp_dds.fit.qmsg
...\..\prev_cmp_dds.map.qmsg
...\..\prev_cmp_dds.qmsg
...\..\prev_cmp_dds.sta.qmsg
...\dds.asm.rpt
...\dds.bdf
...\dds.done
...\dds.dpf
...\dds.fit.rpt
...\dds.fit.smsg
...\dds.fit.summary
...\dds.flow.rpt
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sof
...\dds.sta.rpt
...\dds.sta.summary
...\incremental_db\compiled_partitions\dds.root_partition.cmp.cdb
...\..............\...................\dds.root_partition.cmp.dfp
...\..............\...................\dds.root_partition.cmp.hdb
...\..............\...................\dds.root_partition.cmp.kpt
...\..............\...................\dds.root_partition.cmp.logdb
...\..............\...................\dds.root_partition.cmp.rcfdb
...\..............\...................\dds.root_partition.cmp.re.rcfdb
...\..............\...................\dds.root_partition.map.cdb
...\..............\...................\dds.root_partition.map.dpi
...\..............\...................\dds.root_partition.map.hdb
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