VHDL-FPGA-Verilog List Page 765

VHDL-FPGA-Verilog list

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jishuqiyuchufaqi Downloaded：0: a fpga project
Date : 2025-07-03 Size : 1.88mb User : 陈妍
LD_Lect_5 Downloaded：0: Lectures in Logic Design and Computer Architectures
Date : 2025-07-03 Size : 817kb User : Salah
lab2_solution Downloaded：0: Light water-based platform designed ANVYL, VHDL
Date : 2025-07-03 Size : 549kb User : 张三
lab4_solution Downloaded：0: ANVYL own example, counter design, VHDL language.
Date : 2025-07-03 Size : 745kb User : wei
zidongshouhuoji Downloaded：0: Design a vending machine control system. The system is able to complete the storage of cargo information, process control coin handling, balance calculation, display and other functions. You can manage four kinds of good
Date : 2025-07-03 Size : 2kb User : 武文
xilinx_ddr_verilog Downloaded：0: Xilinx DDR controller source code (including simulation and documentation), DDR is mt46v4m16.
Date : 2025-07-03 Size : 128kb User : 刘佳庆
altera_ddr_verilog Downloaded：0: The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
Date : 2025-07-03 Size : 736kb User : 刘佳庆
traffic-light Downloaded：0: traffic light
Date : 2025-07-03 Size : 1kb User : 杜松
lattice_ddr_verilog-for-orca4 Downloaded：0: The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
Date : 2025-07-03 Size : 601kb User : 刘佳庆
CODE_GEN Downloaded：0: FPGA-based GPS receiver complete code of the spreading code generator design using verilog language
Date : 2025-07-03 Size : 1kb User : 刘先生
shape Downloaded：0: FPGA-based shaping filter code, which included incentives files using verilog write
Date : 2025-07-03 Size : 1.78mb User : 刘先生
BCH_EN Downloaded：0: FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
Date : 2025-07-03 Size : 4.36mb User : 刘先生

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