VHDL-FPGA-Verilog List Page 761

VHDL-FPGA-Verilog list

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cpu-design Downloaded：0: CPU design is realized by VHDL Language, the project contains the test waveform. Contains the CPU design documents, such as directives format, instructions for each function module and test sequence. The project can run
Date : 2025-07-03 Size : 1.53mb User : yuuuuuu
sc_computer_student Downloaded：0: Single-cycle CPU, need to add some code, DE2 board, altera engineering environment
Date : 2025-07-03 Size : 7.73mb User : 郭成
NIOS_II_ Downloaded：0: NIOSii common errors and solutions, using EClipse IDE error in the console and soft-core FPGA create other issues
Date : 2025-07-03 Size : 13kb User : lishh
fpga_spi Downloaded：0: Using FPGA SPI interface, and the FBI STM32 SPI hardware debugging has been successful
Date : 2025-07-03 Size : 1.4mb User : lishh
uart_io_test Downloaded：0: verilog achieve uart, on icore2 can test the code is the prerogative of the students, I modified the baud section. Reset section
Date : 2025-07-03 Size : 4.97mb User : 郭稳
image-scaling--based-on-the-verilog Downloaded：0: Compressed file contains rich image scaling algorithm, written by Verilog language, and contains the corresponding PDF files.
Date : 2025-07-03 Size : 5.95mb User : 林传阳
pipeline_cpu Downloaded：0: 1) MIPS architecture 2) five line 3) to support the MIPS R, I, J three kinds of instruction, a total of twenty. 4) connotation PDF tutorials, project files and incentives
Date : 2025-07-03 Size : 1.07mb User : y
SPI_slave Downloaded：0: spi slave mode
Date : 2025-07-03 Size : 1kb User : 骆钦榕
spi Downloaded：0: spi slave mode
Date : 2025-07-03 Size : 2kb User : 骆钦榕
dig_clk Downloaded：0: digital clock
Date : 2025-07-03 Size : 899kb User : 钱春雷
costas_DPSK Downloaded：0: Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 799.617Hz
Date : 2025-07-03 Size : 2kb User : 小胡萝卜夏天
VHDL Downloaded：0: There is a real crossroads to set something, the north-south trunk road in both directions, to ensure the safe passage of vehicles at every entrance of each trunk group set up two digital display devices and four sets of
Date : 2025-07-03 Size : 914kb User : leitao

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