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pipeline_cpu

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-06-09
  • Size : 1.07mb
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  • Author :y**
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Introduction - If you have any usage issues, please Google them yourself
1) MIPS architecture 2) five line 3) to support the MIPS R, I, J three kinds of instruction, a total of twenty. 4) connotation PDF tutorials, project files and incentives
Packet file list
(Preview for download)


pipeline_cpu
............\bench
............\.....\mipspipe_tb.v
............\doc
............\...\mips.png
............\...\Pipelined MIPS design.pdf
............\model
............\quartus
............\.......\mipstop.qpf
............\.......\mipstop.qsf
............\.......\mipstop.qws
............\.......\output_files
............\.......\............\mipstop.done
............\.......\............\mipstop.fit.smsg
............\.......\............\mipstop.jdi
............\.......\............\mipstop.pin
............\.......\............\mipstop.sof
............\read me.txt
............\src
............\...\adder.v
............\...\ALU.v
............\...\alu_decode.v
............\...\controller.v
............\...\controller.v.bak
............\...\datapath.v
............\...\datapath.v.bak
............\...\d_mem.v
............\...\eqcmp.v
............\...\eqcmp.v.bak
............\...\flopenr.v
............\...\flopenrc.v
............\...\flopr.v
............\...\floprc.v
............\...\hazard.v
............\...\hazard.v.bak
............\...\imemfile.dat
............\...\i_mem.v
............\...\main_decode.v
............\...\main_decode.v.bak
............\...\mipspipe.v
............\...\mipspipe.v.bak
............\...\mipstop.ipinfo
............\...\mipstop.v
............\...\mipstop.v.bak
............\...\mux2.v
............\...\mux3.v
............\...\reg_file.v
............\...\shift_left_2.v
............\...\sign_ext.v
............\vcs
............\...\batch.cpu
............\...\cpu
............\...\cpu_tb.f
............\...\default
............\...\imemfile.dat
............\...\verdi-proj
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