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VHDL-FPGA-Verilog list
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I2C
Downloaded:0
IIC bus
Date
: 2025-07-01
Size
: 5kb
User
:
guangngqiang
USB2.0
Downloaded:0
USB2 module
Date
: 2025-07-01
Size
: 215kb
User
:
guangngqiang
CRC
Downloaded:0
crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input.
Date
: 2025-07-01
Size
: 10kb
User
:
guangngqiang
2ASK
Downloaded:0
FPGA implementation using Altera modulation and demodulation of 2ASK, containing detailed notes and complete project
Date
: 2025-07-01
Size
: 57kb
User
:
汪少锋
cic_cq
Downloaded:0
In the Altera platform using Verilog hardware description language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
Date
: 2025-07-01
Size
: 1.13mb
User
:
汪少锋
cic_cz
Downloaded:0
In the Altera platform using Verilog hardware description language CIC interpolation filter, through the simulation in Modelsim software, including the complete project code, can be directly downloaded to the FPGA operat
Date
: 2025-07-01
Size
: 1.04mb
User
:
汪少锋
dds
Downloaded:0
The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim software, already contains all the code and engineer
Date
: 2025-07-01
Size
: 678kb
User
:
汪少锋
spi
Downloaded:0
SPI interface slave verilog
Date
: 2025-07-01
Size
: 1kb
User
:
王一
PLL_Inst
Downloaded:0
Phase-Locked Loop-based design
Date
: 2025-07-01
Size
: 1kb
User
:
王一
ds18b20
Downloaded:0
Making use of DS18B20 digital thermometer temperature sensor in the Altera FPGA, and digital tube display. The language used for the Verilog, including all the projects and files, can be used directly.
Date
: 2025-07-01
Size
: 6.69mb
User
:
汪少锋
uart_tx_rx
Downloaded:0
Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code
Date
: 2025-07-01
Size
: 14.66mb
User
:
汪少锋
PWM_music
Downloaded:0
In the Altera FPGA platform, using Verilog language to achieve the buzzer music, FPGA music code and engineering including music theory and implementation of Verilog, has been tested, can be downloaded directly to the FP
Date
: 2025-07-01
Size
: 659kb
User
:
汪少锋
«
1
2
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.54
.55
.56
.57
.58
759
.60
.61
.62
.63
.64
...
4310
»
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