VHDL-FPGA-Verilog List Page 769

VHDL-FPGA-Verilog list

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fangbo--quartus Downloaded：0: VHDL program language to write the FPGA to produce square wave, for reference
Date : 2025-07-03 Size : 1kb User : Smith Jick
pinlvji Downloaded：0: The digital frequency meter To detect the 1Hz-10KHz frequency signal and overrange alert
Date : 2025-07-03 Size : 4.39mb User : 10086
pinlvjitest Downloaded：0: Digital frequency meter testbench testing procedures, and the digital frequency meter with the use of the program on the input signal and the test signal is provided.
Date : 2025-07-03 Size : 7kb User : 10086
led Downloaded：0: LED decoder circuit design, implementation, LED display, and the scanning circuit. The program uses a common cathode. The main points to be able to automatically adapt to the large ones scanning circuit
Date : 2025-07-03 Size : 4.38mb User : 10086
ledtest Downloaded：0: Digital decoding circuit test program, using modlesim tested. The documents and led.rar with testing, if you do not test, without having to download the file. led.rar using a modular design, vhdl divided into several fil
Date : 2025-07-03 Size : 61kb User : 10086
seq_detector Downloaded：0: The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test source program.
Date : 2025-07-03 Size : 1kb User : 10086
adder16.v Downloaded：1: This to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
Date : 2025-07-03 Size : 1kb User : liuyang
addercs16.v Downloaded：0: It is 16 bits verilog write their own code to carry select adder, if a useful fell free to download
Date : 2025-07-03 Size : 1kb User : liuyang
multiplier.v Downloaded：0: Verilog still write their own code of an 8* 8 multiplier, so please download, thank you
Date : 2025-07-03 Size : 1kb User : liuyang
fulladder.v Downloaded：1: Write your own full adder verilog code, please download. If you have questions, please give me a comment
Date : 2025-07-03 Size : 1kb User : liuyang
code Downloaded：0: Five people voting, voting machine design a five master asynchronous clear and latch mechanism
Date : 2025-07-03 Size : 1kb User : 张双图
code Downloaded：0: Design a synchronous binary counter twenty-four understanding count the trigger synchronization mechanism, master synchronous trigger VHDL description method and asynchronous clear description of the method.
Date : 2025-07-03 Size : 1kb User : 张双图

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