ANVYL own example, counter design, VHDL language.

lab4_solution\clock_divider.vhd
.............\counter.vhd
.............\iseconfig\lab4.projectmgr
.............\.........\main.xreport
.............\lab4.gise
.............\lab4.xise
.............\lab4_计数器设计.pdf
.............\main.lso
.............\main.vhd
.............\main_bitgen.xwbt
.............\main_guide.ncd
.............\myucf.ucf
.............\par_usage_statistics.html
.............\seven_seg_controller.vhd
.............\state_machine.vhd
.............\iseconfig
.............\_xmsgs
lab4_solution

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