VHDL-FPGA-Verilog List Page 730

VHDL-FPGA-Verilog list

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seg Downloaded：0: Four digital tube display, realize the dynamic display of digital tube.Already test, very good!
Date : 2025-06-29 Size : 3.09mb User : 吴宁
i2s_latest Downloaded：0: Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL Dev
Date : 2025-06-29 Size : 5kb User : chen
my_uart2 Downloaded：0: Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Summary -----------
Date : 2025-06-29 Size : 248kb User : chen
vga256 Downloaded：0: This is a VGA-Verilog procedures can be shown on the display 8 colors
Date : 2025-06-29 Size : 549kb User : lulei
PCIIP-core Downloaded：0: “fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generation. It also generates read and wr
Date : 2025-06-29 Size : 1.86mb User : chen
sp605_pcie_13.2 Downloaded：0: input user_clk, input user_reset, input user_lnk_up, // Tx input [5:0] tx_buf_av, input tx_cfg_req, output tx_cfg_gnt, input tx_err_drop, input s_axis_tx_tready, output [31:0] s_axis_tx_tdata, output [3:0] s_axis_tx_tst
Date : 2025-06-29 Size : 364kb User : chen
verilog_cordic_core Downloaded：0: Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Arithmetic core Language: V
Date : 2025-06-29 Size : 351kb User : chen
EDK_adv212 Downloaded：0: adv 212 controller, using xilinx edk
Date : 2025-06-29 Size : 2.39mb User : Quenii
LCD12864 Downloaded：0: The program is used to control CPLD 12864，link:http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251 to view
Date : 2025-06-29 Size : 331kb User : CHEN
lcd1602 Downloaded：0: CPLD to control the program by 1602, the display see http://zhuxiangqing.blog.163.com/album/# m = 2 & aid = 264724219 & pid = 8732102150
Date : 2025-06-29 Size : 219kb User : CHEN
axi_ad9361_tx_channel Downloaded：0: AD9361 using hardware description languages Verilog code that chip
Date : 2025-06-29 Size : 2kb User : 何晨光
dds Downloaded：0: Using hardware description languages Verilog implementation of DDS converter code
Date : 2025-06-29 Size : 1kb User : 何晨光

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