VHDL-FPGA-Verilog List Page 725

VHDL-FPGA-Verilog list

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fulladder.tar Downloaded：0: Verilog Code for Full Adder circuit with Testbench file
Date : 2025-06-29 Size : 1kb User : Dhaval
basicgates Downloaded：0: Verilog Code for Basic Gates implementation with testbench
Date : 2025-06-29 Size : 76kb User : Dhaval
mux4_1 Downloaded：0: Verilog Code for 4*1 Multiplexer with testbench file
Date : 2025-06-29 Size : 12kb User : Dhaval
8bit_decoder Downloaded：0: Verilog code for 3*8 Decoder Circuit with testbench file
Date : 2025-06-29 Size : 8kb User : Dhaval
UART_RX Downloaded：0: This learn from others with FIFO Verilog code for everyone to share, learn together
Date : 2025-06-29 Size : 732kb User : 汪静
baud_gen Downloaded：0: Uart is a universal serial data bus, used for asynchronous communication. The bus bidirectional communication, can realize the full duplex transmission and reception. In embedded design. The code for the UART baud rate g
Date : 2025-06-29 Size : 1kb User : 方仔
THP Downloaded：2: THP algorithm MATLAB procedures, can give a good teaching beginners
Date : 2025-06-29 Size : 17kb User : Dexter
CNT10 Downloaded：0: decimal counter vhdl design, simulation tests correctly, can be used.
Date : 2025-06-29 Size : 1kb User : 高立新
adder4bit Downloaded：0: VHDL design of four adders, a simulation test correctly, you can use
Date : 2025-06-29 Size : 125kb User : 高立新
LS194 Downloaded：0: 194 IC VHDL design, simulation tests correctly, can be used.
Date : 2025-06-29 Size : 1kb User : 高立新
ls74160 Downloaded：0: 160 IC VHDL design, simulation tests correctly, can be used.
Date : 2025-06-29 Size : 1kb User : 高立新
LS7400 Downloaded：0: 7400 IC VHDL design, simulation tests correctly, can be used.
Date : 2025-06-29 Size : 143kb User : 高立新

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