VHDL-FPGA-Verilog List Page 721

VHDL-FPGA-Verilog list

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UART-IP-based-on-queue Downloaded：0: Queue-based transmission of UART IP core procedures have been debugging can be used directly.
Date : 2025-06-29 Size : 10kb User : 瞿盛
SPDIF-interface-IP-core Downloaded：0: The program SPDIF digital audio interface has been written in the form of common IP core.
Date : 2025-06-29 Size : 43kb User : 瞿盛
HSDI-communcation-interface-IP Downloaded：0: FPGA-based programs HSDI interfaces, debug available.
Date : 2025-06-29 Size : 6kb User : 瞿盛
CAN_VHD.ZIP Downloaded：1: CAN VHDL Controller Area Network en languge VHDL CAN VHDL Opencore
Date : 2025-06-29 Size : 50kb User : Mengkoung
traffic Downloaded：0: traffic light control by FPGA Quartos
Date : 2025-06-29 Size : 1kb User : amin
Blockramhist Downloaded：0: block RAM hist
Date : 2025-06-29 Size : 1kb User :
51cpldDesignSource Downloaded：0: fpga+ c51 design source, Collections.The Internet are not recommended several such source code download
Date : 2025-06-29 Size : 51kb User : 王蒙
EEPROM Downloaded：0: EEPROM write verilog written operating procedures have water lights display
Date : 2025-06-29 Size : 298kb User : maowentao
aurora_bram Downloaded：0: Xilinx SP605 Evaluation Kit Aurora IP core functional verification debugging source code and chipscope verified
Date : 2025-06-29 Size : 2.96mb User :
K7DDR3 Downloaded：0: About debugger on K7 board ddr3, with the verilog language written
Date : 2025-06-29 Size : 13.94mb User : taiping
12345PS2 Downloaded：0: PS2 keyboard interface VHDL program, after a rigorous simulation, of great reference value.
Date : 2025-06-29 Size : 375kb User : 崔凯华
HDB3 Downloaded：0: HDB3 VHDL keyboard interface program, after a rigorous simulation, of great reference value.
Date : 2025-06-29 Size : 254kb User : 崔凯华

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