VHDL-FPGA-Verilog List Page 720

VHDL-FPGA-Verilog list

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proje2 Downloaded：0: it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
Date : 2025-06-29 Size : 1kb User : Arash
proje Downloaded：0: its ALU using VHDL. its parameter have 16 bits and doing logical and arithmetic functions
Date : 2025-06-29 Size : 1kb User : Arash
proje4 Downloaded：0: It is 8 bit divisor. it is restoring algorithm implementation.
Date : 2025-06-29 Size : 2kb User : Arash
proje3 Downloaded：0: it is ALU using VHDL language. it has inputs with 3 bits.
Date : 2025-06-29 Size : 1kb User : Arash
project5_UART Downloaded：0: It is UART protocol in VHDL. it has two files. one is transmitter and one is receiver.
Date : 2025-06-29 Size : 2kb User : Arash
non--restoring Downloaded：0: it is dividing non restoring algorithm implementation using verilog language.
Date : 2025-06-29 Size : 1kb User : Arash
da_80m_10m Downloaded：1: the test program of AD9747，FPGA IS SP6
Date : 2025-06-29 Size : 12.18mb User : 张海军
uartverilog Downloaded：0: With verilog prepared by the serial communication program, really good, recommend it to everyone learning together about. Hoping to help.
Date : 2025-06-29 Size : 304kb User : 张东豪
i2c_master Downloaded：0: verlog i2c master
Date : 2025-06-29 Size : 2kb User : jimmy
i2c_slave Downloaded：0: i2c slave verilog code
Date : 2025-06-29 Size : 3kb User : jimmy
LAB7_1 Downloaded：0: LAB 7 VERILOG DE2-115
Date : 2025-06-29 Size : 1.79mb User : luxen
LAB7_3 Downloaded：0: lab7 part 3 verilog de2-115
Date : 2025-06-29 Size : 2.84mb User : luxen

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