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  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-08-08
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LAB 7 VERILOG DE2-115
Packet file list
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LAB7_1\LAB7_1.qpf
......\LAB7_1.qsf
......\db\LAB7_1.db_info
......\..\LAB7_1.map.qmsg
......\..\LAB7_1.hif
......\..\LAB7_1.map.rdb
......\..\LAB7_1.cbx.xml
......\..\LAB7_1.ipinfo
......\..\prev_cmp_LAB7_1.qmsg
......\..\LAB7_1.hier_info
......\..\LAB7_1.rtlv_sg_swap.cdb
......\..\LAB7_1.smart_action.txt
......\..\LAB7_1.lpc.txt
......\..\logic_util_heursitic.dat
......\..\LAB7_1.lpc.html
......\..\LAB7_1.lpc.rdb
......\..\LAB7_1.pre_map.hdb
......\..\LAB7_1.smp_dump.txt
......\..\LAB7_1.map_bb.logdb
......\..\LAB7_1.sgdiff.cdb
......\..\LAB7_1.sgdiff.hdb
......\..\LAB7_1.eda.qmsg
......\..\LAB7_1.root_partition.map.reg_db.cdb
......\..\LAB7_1.sld_design_entry.sci
......\..\LAB7_1.npp.qmsg
......\..\LAB7_1.sgate.nvd
......\..\LAB7_1.rtlv.hdb
......\..\LAB7_1.map.ammdb
......\..\LAB7_1.rtlv_sg.cdb
......\..\LAB7_1.map.kpt
......\..\LAB7_1.cmp_merge.kpt
......\..\.cmp.kpt
......\..\LAB7_1.map.cdb
......\..\LAB7_1.map.hdb
......\..\LAB7_1.sld_design_entry_dsc.sci
......\..\LAB7_1.map_bb.cdb
......\..\LAB7_1.map_bb.hdb
......\..\LAB7_1.cmp.hdb
......\..\LAB7_1.sgate_sm.nvd
......\..\LAB7_1.map.logdb
......\..\LAB7_1.sgate_sm_bdd.nvd
......\..\LAB7_1.cmp.rdb
......\..\LAB7_1.map.bpm
......\..\LAB7_1.pti_db_list.ddb
......\..\LAB7_1.tis_db_list.ddb
......\ff_d.v
......\LAB7_1.v
......\output_files\LAB7_1.map.summary
......\............\LAB7_1.done
......\............\LAB7_1.pin
......\............\LAB7_1.fit.smsg
......\............\LAB7_1.fit.summary
......\............\LAB7_1.jdi
......\............\LAB7_1.sof
......\............\Chain1.cdf
......\............\LAB7_1.cdf
......\............\LAB7_1.fit.rpt
......\............\LAB7_1.asm.rpt
......\............\LAB7_1.sta.summary
......\............\LAB7_1.sta.rpt
......\............\LAB7_1.map.rpt
......\............\LAB7_1.eda.rpt
......\............\LAB7_1.flow.rpt
......\LAB7_1.v.bak
......\incremental_db\compiled_partitions\LAB7_1.db_info
......\..............\...................\LAB7_1.root_partition.map.hbdb.hb_info
......\..............\...................\LAB7_1.root_partition.map.hbdb.cdb
......\..............\...................\LAB7_1.root_partition.map.hbdb.hdb
......\..............\...................\LAB7_1.root_partition.map.hbdb.sig
......\..............\...................\LAB7_1.root_partition.map.dpi
......\..............\...................\LAB7_1.root_partition.map.cdb
......\..............\...................\LAB7_1.root_partition.cmp.dfp
......\..............\...................\LAB7_1.root_partition.map.hdb
......\..............\...................\LAB7_1.root_partition.cmp.logdb
......\..............\...................\LAB7_1.root_partition.cmp.kpt
......\..............\...................\LAB7_1.root_partition.map.kpt
......\..............\README
......\part2.v
......\part2.v.bak
......\LAB7_1.qsf.bak
......\simulation\modelsim\LAB7_1_modelsim.xrf
......\..........\........\LAB7_1_7_1200mv_85c_slow.vo
......\..........\........\LAB7_1_7_1200mv_0c_slow.vo
......\..........\........\LAB7_1_min_1200mv_0c_fast.vo
......\..........\........\LAB7_1.vo
......\..........\........\LAB7_1_7_1200mv_85c_v_slow.sdo
......\..........\........\LAB7_1_7_1200mv_0c_v_slow.sdo
......\..........\........\LAB7_1_min_1200mv_0c_v_fast.sdo
......\..........\........\LAB7_1_v.sdo
......\..........\........\LAB7_1.sft
......\..........\qsim\LAB7_1_modelsim.xrf
......\..........\....\LAB7_1.vo
......\..........\....\LAB7_1.do
......\..........\....\transcript
......\..........\....\work\_info
......\..........\....\....\_vmake
......\..........\....\....\@l@a@b7_1\_primary.vhd
......\..........\....\....\.........\verilog.psm
......\..........\....\....\.........\verilog.prw
......\..........\....\....\.........\_primary.dbs
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