VHDL-FPGA-Verilog List Page 734

VHDL-FPGA-Verilog list

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multifunction_digita Downloaded：0: There FPGA-based design and implementation of multi-functional digital clock containing detailed Verilog HDL source code and its function are: time setting, time display, stopwatch, frequency, date setting, date, etc.
Date : 2025-06-30 Size : 3.14mb User : 荼皞
Verilog-RS232 Downloaded：0: This procedure is simulated in FPGA RS232 serial port, and in the debugging success
Date : 2025-06-30 Size : 3kb User : yz
counter Downloaded：0: a counter can increase and decline,and simulation the function of the counter
Date : 2025-06-30 Size : 406kb User : 云在阴天
2009511191253884-(1) Downloaded：0: Kiki on fpga 1602 fpga lighting source code 1602 based lighting source code in fpga 1602 lighting source code
Date : 2025-06-30 Size : 182kb User : zhan
counter_16 Downloaded：0: Based on the development of mold counter ISE14.7 16, FPGA development board used for the Spartan 3E Start Kit
Date : 2025-06-30 Size : 1.46mb User : zhanghust
acdc_fpga Downloaded：0: phrase bus
Date : 2025-06-30 Size : 343kb User : 罗望
CoG Downloaded：1: Semi-functional FSM and ROM for Xilinx CPLD to drive ST7565R based off Digikey example
Date : 2025-06-30 Size : 1.02mb User : Mac
ex16 Downloaded：0: word show
Date : 2025-06-30 Size : 2.46mb User : 罗望
Prescaler-to-use-VHDL-design Downloaded：0: This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, including even frequency, non-50 duty cycle and 50 duty cycle odd frequency, half-integer (N+0.5) Divide, fractional, fractional and int
Date : 2025-06-30 Size : 332kb User : liufei
module-dapeng Downloaded：0: This code based on FPGA to realize the timing range: 00 00 00 ~ 59 59 "99," according to the function of the maximum time for 59 minutes and 59 seconds.Digital stopwatch timing accuracy is 10 ms.Display works: a, with ei
Date : 2025-06-30 Size : 4kb User : 董婷
FPGA1 Downloaded：0: Multiplexer, 4 channel 8 bits with three states type
Date : 2025-06-30 Size : 1.21mb User : 董婷
FPGA2 Downloaded：0: Based on the FPGA 8-bit input, three output high priority encoder
Date : 2025-06-30 Size : 231kb User : 董婷

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