VHDL-FPGA-Verilog List Page 736

VHDL-FPGA-Verilog list

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vga Downloaded：0: This article contains a VGA verilog code and testing procedures
Date : 2025-06-30 Size : 135kb User : 钱红
CANBUS Downloaded：0: This article contains the CAN verilog code and testing procedures
Date : 2025-06-30 Size : 1.01mb User : 钱红
traffic-light-design Downloaded：0: ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.
Date : 2025-06-30 Size : 3.89mb User : 逍遥一笑
frequency Downloaded：0: verilog prepared dual-range frequency meter and simulation test program, using 500MHz system clock
Date : 2025-06-30 Size : 3kb User : 薛思洋
frame Downloaded：0: frame synchronization detection code written in verilog and simulation procedures with frame information using a pseudo-random code sequence, and synchronization code 100110
Date : 2025-06-30 Size : 4kb User : 薛思洋
i2c_slave Downloaded：0: verilog HDL I2C Slave function module with address matching and eight 8-bit data registers and write.
Date : 2025-06-30 Size : 373kb User : joans
msp430f5529_digital_clock Downloaded：0: This a digital clock routine of msp430f5529, it has digital clock, pointer type clock, backlight adjustment and a series of perfect functions
Date : 2025-06-30 Size : 2.5mb User : tanxiaoyao
msp430f5529_accelerater Downloaded：0: msp430f5529 development board accelerometer experimental procedure can experiment accelerometer, which prepared two simple little game using accelerometer
Date : 2025-06-30 Size : 2.5mb User : tanxiaoyao
msp430f5529_airship_game Downloaded：0: msp430f5529 SCM is very classic spaceship unblinded game, use LCD10264 display, can be used to learn UI 430 LCD display technology
Date : 2025-06-30 Size : 2.53mb User : tanxiaoyao
msp430f5529_usb_pc Downloaded：0: A single chip computer and PC through the serial port communication experiment, single-chip model is msp430f5529
Date : 2025-06-30 Size : 2.49mb User : tanxiaoyao
msp430f5529_usb_rw Downloaded：0: 430 singlechip USB read and write test, based on the msp430f5529 development board, you can learn about it
Date : 2025-06-30 Size : 2.52mb User : tanxiaoyao
cpu_design Downloaded：0: FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Date : 2025-06-30 Size : 2.32mb User : leo

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