input user_clk, input user_reset, input user_lnk_up, // Tx input [5:0] tx_buf_av, input tx_cfg_req, output tx_cfg_gnt, input tx_err_drop, input s_axis_tx_tready, output [31:0] s_axis_tx_tdata, output [3:0] s_axis_tx_tstrb, output [3:0] s_axis_tx_tuser, output s_axis_tx_tlast, output s_axis_tx_tvalid, // Rx output rx_np_ok, input [31:0] m_axis_rx_tdata, input [3:0] m_axis_rx_tstrb, input m_axis_rx_tlast, input m_axis_rx_tvalid, output m_axis_rx_tready, input [21:0] m_axis_rx_tuser, // Flow Control input [11:0] fc_cpld, input [7:0] fc_cplh, input [11:0] fc_npd, input [7:0] fc_nph, input [11:0] fc_pd, input [7:0] fc_ph, output [2:0] fc_sel, input [31:0] cfg_do, input cfg_rd_w

sp605_pcie_13.2\s6_pcie_v2_2\doc\ds801_s6_pcie.pdf
...............\............\...\s6_pcie_v2_2_vinfo.html
...............\............\...\ug672_S6_IntEndptBlock_PCIe.pdf
...............\............\example_design\pcie_app_s6.v
...............\............\..............\PIO.v
...............\............\..............\PIO_32_RX_ENGINE.v
...............\............\..............\PIO_32_TX_ENGINE.v
...............\............\..............\PIO_EP.v
...............\............\..............\PIO_EP_MEM.v
...............\............\..............\PIO_EP_MEM_ACCESS.v
...............\............\..............\PIO_TO_CTRL.v
...............\............\..............\xilinx_pcie_1_1_ep_s6.v
...............\............\..............\xilinx_pcie_1_lane_ep_xc6slx45t-fgg484-3.ucf
...............\............\implement\implement.bat
...............\............\.........\implement.sh
...............\............\.........\xst.prj
...............\............\.........\xst.scr
...............\............\s6_pcie_readme.txt
...............\............\.imulation\dsport\gtx_drp_chanalign_fix_3752_v6.v
...............\............\..........\......\gtx_rx_valid_filter_v6.v
...............\............\..........\......\gtx_tx_sync_rate_v6.v
...............\............\..........\......\gtx_wrapper_v6.v
...............\............\..........\......\pcie_2_0_rport_v6.v
...............\............\..........\......\pcie_2_0_v6_rp.v
...............\............\..........\......\pcie_brams_v6.v
...............\............\..........\......\pcie_bram_top_v6.v
...............\............\..........\......\pcie_bram_v6.v
...............\............\..........\......\pcie_clocking_v6.v
...............\............\..........\......\pcie_gtx_v6.v
...............\............\..........\......\pcie_pipe_lane_v6.v
...............\............\..........\......\pcie_pipe_misc_v6.v
...............\............\..........\......\pcie_pipe_v6.v
...............\............\..........\......\pcie_reset_delay_v6.v
...............\............\..........\......\pcie_upconfig_fix_3451_v6.v
...............\............\..........\......\pci_exp_usrapp_cfg.v
...............\............\..........\......\pci_exp_usrapp_com.v
...............\............\..........\......\pci_exp_usrapp_pl.v
...............\............\..........\......\pci_exp_usrapp_rx.v
...............\............\..........\......\pci_exp_usrapp_tx.v
...............\............\..........\......\xilinx_pcie_2_0_rport_v6.v
...............\............\..........\functional\board.f
...............\............\..........\..........\board.v
...............\............\..........\..........\isim_cmd.tcl
...............\............\..........\..........\simulate_isim.bat
...............\............\..........\..........\simulate_isim.sh
...............\............\..........\..........\simulate_mti.do
...............\............\..........\..........\simulate_ncsim.sh
...............\............\..........\..........\simulate_vcs.sh
...............\............\..........\..........\sys_clk_gen.v
...............\............\..........\..........\sys_clk_gen_ds.v
...............\............\..........\..........\wave.do
...............\............\..........\..........\wave.sv
...............\............\..........\..........\wave.tcl
...............\............\..........\..........\wave.wcfg
...............\............\..........\tests\tests.v
...............\............\.ource\axi_basic_rx.v
...............\............\......\axi_basic_rx_null_gen.v
...............\............\......\axi_basic_rx_pipeline.v
...............\............\......\axi_basic_top.v
...............\............\......\axi_basic_tx.v
...............\............\......\axi_basic_tx_pipeline.v
...............\............\......\axi_basic_tx_thrtl_ctl.v
...............\............\......\gtpa1_dual_wrapper.v
...............\............\......\gtpa1_dual_wrapper_tile.v
...............\............\......\pcie_brams_s6.v
...............\............\......\pcie_bram_s6.v

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