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VHDL-FPGA-Verilog list
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Verilog_HDL_
Downloaded:0
Verilog HDL
Date
: 2025-11-18
Size
: 257kb
User
:
张金梅
diver
Downloaded:0
VHDL
Date
: 2025-11-18
Size
: 552kb
User
:
笨蛋
Baseband_line_code
Downloaded:0
Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code
Date
: 2025-11-18
Size
: 667kb
User
:
tanisaber
FPGA
Downloaded:0
FPGA design (design and techniques). Very very useful, we want to help.
Date
: 2025-11-18
Size
: 254kb
User
:
李晨辉
PS2_keyboard
Downloaded:0
implement a PS/2 keyboard host controller by using verilog HDL.
Date
: 2025-11-18
Size
: 81kb
User
:
chalis
rd_wr_generate
Downloaded:0
generate the address of reading and writing
Date
: 2025-11-18
Size
: 6kb
User
:
吴朱佳
Miller
Downloaded:0
Curriculum design, schematics, VHDL language to describe the encoding and decoding
Date
: 2025-11-18
Size
: 2.92mb
User
:
谢能燕
DigitalClock
Downloaded:0
Digital clock, set the number of keys, to complete a time, sub-bit flash time adjustment function.
Date
: 2025-11-18
Size
: 1kb
User
:
李月天
synchronous
Downloaded:0
1:10 string and conversion, including the simultaneous detection and word alignment.
Date
: 2025-11-18
Size
: 1kb
User
:
yuzhen
eda1
Downloaded:0
digital clock
Date
: 2025-11-18
Size
: 1.44mb
User
:
小李
DE0_SDRAM
Downloaded:0
ALTERA DE0 SDRAM
Date
: 2025-11-18
Size
: 7.46mb
User
:
柳春青
hspice1
Downloaded:0
Circuit design and simulation tools hspice important use of documents. Without a teacher
Date
: 2025-11-18
Size
: 1.35mb
User
:
yuzhen
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