VHDL-FPGA-Verilog List Page 2984

VHDL-FPGA-Verilog list

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AVR Downloaded：0: VHDL implementation using AVR, IPcode the AVR
Date : 2025-11-19 Size : 66kb User : liwei
SPI Downloaded：0: Using VHDL implementation spi, IPcode the spi
Date : 2025-11-19 Size : 50kb User : liwei
RISC_CPU Downloaded：0: Using VHDL implementation risc cpu, IPcode the risc cpu
Date : 2025-11-19 Size : 561kb User : liwei
Xilinx_FPGA_for_ADC_samp Downloaded：0: Xilinx FPGA development board of the ADC sample source code
Date : 2025-11-19 Size : 7kb User : liwei
ic_flow Downloaded：0: IC Flow power point presentation useful for the designing of vlsi chips
Date : 2025-11-19 Size : 1.32mb User : raj
cpld_sy03091 Downloaded：0: cpld epm7128 information source development board schematics
Date : 2025-11-19 Size : 1.22mb User : zhaoshihai
fenpin Downloaded：0: A sub-frequency program FPGA, FPGA clock frequency asked 100MHz, for 100 million frequency.
Date : 2025-11-19 Size : 2kb User : 陶志颖
dds_last Downloaded：0: Prepared using VHDL DDS, practical simplicity, conducive to learning exchange
Date : 2025-11-19 Size : 642kb User : zhuhaotian
elevator Downloaded：0: Program for elevator controling by using verylog HDL
Date : 2025-11-19 Size : 155kb User : Rick
soccorrobo Downloaded：0: SOCCER-ROBOT DESIGN ON FPGA source code. The robot is triangle width 20 cm. height 15 cm. have 3 motor and control by L298 chip.
Date : 2025-11-19 Size : 13kb User : Noah
jiaotongdeng Downloaded：0: We design a simple traffic light intersection. West and East, and North-South traffic lights both directions, both through the digital control and the indicator indicates the current state. Traffic in both directions set
Date : 2025-11-19 Size : 28kb User : shenlina
bcdmaxianshiyiyunsuan Downloaded：0: Design a rounded discrimination circuit, the input 8421BCD code requirements when the input is greater than or equal to 5, the discrimination circuit output is 1, otherwise 0.
Date : 2025-11-19 Size : 760kb User : shenlina

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