VHDL-FPGA-Verilog List Page 2982

VHDL-FPGA-Verilog list

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dayclock Downloaded：0: EDA electronic clock。include the second clock,alarm clock.
Date : 2025-11-19 Size : 980kb User : sunying
div Downloaded：0: sub-divided function,I have debug it right.It is helpful to you
Date : 2025-11-19 Size : 126kb User : xiaowang
BEE Downloaded：0: Verilog HDL experiment code for bee. Debug it right.
Date : 2025-11-19 Size : 81kb User : xiaowang
moore Downloaded：0: moore state machine code of verilog HDL.Debug it right.
Date : 2025-11-19 Size : 289kb User : xiaowang
miaobiao Downloaded：0: clock using counter code of verilog HDL.I debug it right
Date : 2025-11-19 Size : 391kb User : xiaowang
e1framerdeframer_latest Downloaded：0: E1 signal to achieve a framing, CRC checking function, two-way communication, duplex work, the actual test by
Date : 2025-11-19 Size : 35kb User : 宋珂
tdm_latest[1] Downloaded：0: TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange
Date : 2025-11-19 Size : 794kb User : 宋珂
hdlc_latest[1] Downloaded：0: HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
Date : 2025-11-19 Size : 560kb User : 宋珂
fulladder Downloaded：0: simulation full adder using vhdl
Date : 2025-11-19 Size : 7.69mb User : vu minh duc
qdq Downloaded：0: FPGA-based multi-Responder, using Verilog language
Date : 2025-11-19 Size : 1kb User : snowy
VHDL380examples Downloaded：0: Vhdl for beginners who have a lot of help, very useful program, it is useful
Date : 2025-11-19 Size : 7.02mb User : 林雅斋
tlc549 Downloaded：0: Chip detailed explanation of the rational use of chips, mainly used for digital-analog conversion
Date : 2025-11-19 Size : 2.02mb User : 林雅斋

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