VHDL-FPGA-Verilog List Page 2992

VHDL-FPGA-Verilog list

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xilinxise10.1edk Downloaded：0: Xilinx ise10.1 edk Xiangjie xilinx training materials to the Chinese translated example of Huawei training materials to Spartan3
Date : 2025-11-18 Size : 13.16mb User : 陈勇
DigitalClock Downloaded：0: The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual
Date : 2025-11-18 Size : 1.27mb User : fushibin
add8 Downloaded：0: It is a counting device with eight-bit that could plus ,subtract ,multiply and divide.
Date : 2025-11-18 Size : 3kb User : 邓
shumaguanxianshi Downloaded：0: It is a displayer control sequence using VHDL language
Date : 2025-11-18 Size : 1kb User : 邓
balucaidhengsheji Downloaded：0: This is a colourful led-light design which can realize different displayer of led-light
Date : 2025-11-18 Size : 3kb User : 邓
Taxi Downloaded：0: EDA curriculum Taximeter the VHDL language design process Taximeter5KM from the valuationthe starting price of 5 yuan1.2 yuan per kilometersensor output pulse is 0.5m monthper 0.5km to change a display, and early show (s
Date : 2025-11-18 Size : 161kb User : 李小璐
shuzizhong Downloaded：0: It is about a design of digital clock,which is comprised a 24 and a 60 counting device and a display device
Date : 2025-11-18 Size : 1.16mb User : 邓
project Downloaded：0: digital clock
Date : 2025-11-18 Size : 354kb User : wb
TIM_DLY_LED Downloaded：0: Controllable single narrow pulse signal power FPGA implemented internal procedures
Date : 2025-11-18 Size : 1kb User : 黄茂琴
IIC Downloaded：0: IIC INTERFCAE DESIGN
Date : 2025-11-18 Size : 2kb User : 何文忠
state Downloaded：0: With positive and negative periodic signals with frequency phase measuring machine FPGA Implementation
Date : 2025-11-18 Size : 1kb User : 黄茂琴
Phase_Meter Downloaded：0: Unsigned band show the periodic signal code phase measurement achieve
Date : 2025-11-18 Size : 1kb User : 黄茂琴

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