VHDL-FPGA-Verilog List Page 2996

VHDL-FPGA-Verilog list

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ETH Downloaded：0: The system top-level module, called the bottom module 4. 4 large modules underlying module: cpu modules, transmit modules, receiver modules, mii module
Date : 2025-11-18 Size : 5kb User : mao
ledcontrol Downloaded：0: FPGA-driven LED static display- File Name: ledcontrol.vhd- Function: decode the output module, LED is connected in a total of Yang
Date : 2025-11-18 Size : 1kb User : mao
plj Downloaded：0: - File Name: PLJ.vhd.- Function: 4 display of equal precision frequency meter.- Last modified date: 2004.4.14.
Date : 2025-11-18 Size : 1kb User : mao
NonPipelined_Design Downloaded：0: VHDL implementation with non-pipelined CPU design
Date : 2025-11-18 Size : 291kb User : hewei
PipelinedCPU Downloaded：0: Using Verilog design language of the line CPU, you can reference.
Date : 2025-11-18 Size : 12.05mb User : hewei
clock Downloaded：0: CLOCK
Date : 2025-11-18 Size : 1kb User : 许诺
digitalcymometer Downloaded：0: digital cymometer design based on vhdl language
Date : 2025-11-18 Size : 786kb User : lxb
trafficlight Downloaded：0: traffic light based on quartusII
Date : 2025-11-18 Size : 549kb User : lxb
decoder38 Downloaded：0: decoder 38 based on quartusII
Date : 2025-11-18 Size : 272kb User : lxb
3fenpin Downloaded：0: divide frequency by 3 based on quartusII
Date : 2025-11-18 Size : 252kb User : lxb
dianziqn Downloaded：0: e-piano based on quartusII and designed by vhdl language
Date : 2025-11-18 Size : 2.33mb User : lxb
FSK_VHDL Downloaded：0: Modulation and demodulation FSK VHDL procedures and simulation
Date : 2025-11-18 Size : 51kb User : joek

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