ALTERA DE0 SDRAM

DE0_SDRAM\Sdram_Control_2Port\transcript
.........\...................\Sdram_Params.h
.........\...................\control_interface.v
.........\...................\Sdram_Controller.v
.........\...................\Sdram_PLL.v
.........\...................\sdr_data_path.v
.........\...................\command.v.bak
.........\...................\command.v
.........\.EG7_LUT\SEG7_LUT_8.v.bak
.........\........\SEG7_LUT_8.v
.........\........\SEG7_LUT.v.bak
.........\........\SEG7_LUT.v
.........\db\SDRAM_HR_HW.fit.qmsg
.........\..\SDRAM_HR_HW.db_info
.........\..\SDRAM_HR_HW.rtlv_sg_swap.cdb
.........\..\SDRAM_HR_HW.rtlv_sg.cdb
.........\..\SDRAM_HR_HW.lpc.txt
.........\..\SDRAM_HR_HW.lpc.html
.........\..\SDRAM_HR_HW.lpc.rdb
.........\..\altsyncram_i2t3.tdf
.........\..\mux_irc.tdf
.........\..\logic_util_heursitic.dat
.........\..\SDRAM_HR_HW.pre_map.hdb
.........\..\SDRAM_HR_HW.cbx.xml
.........\..\SDRAM_HR_HW.smp_dump.txt
.........\..\SDRAM_HR_HW.pre_map.cdb
.........\..\SDRAM_HR_HW.smart_action.txt
.........\..\SDRAM_HR_HW.map_bb.logdb
.........\..\SDRAM_HR_HW.sgdiff.hdb
.........\..\SDRAM_HR_HW.cmp.logdb
.........\..\SDRAM_HR_HW.eco.cdb
.........\..\cntr_pgi.tdf
.........\..\cmpr_lfc.tdf
.........\..\SDRAM_HR_HW.sld_design_entry_dsc.sci
.........\..\prev_cmp_SDRAM_HR_HW.qmsg
.........\..\SDRAM_HR_HW.map.cbp
.........\..\SDRAM_HR_HW.map.cdb
.........\..\SDRAM_HR_HW.map.hdb
.........\..\SDRAM_HR_HW.rtlv.hdb
.........\..\SDRAM_HR_HW.hif
.........\..\SDRAM_HR_HW.cmp.cdb
.........\..\SDRAM_HR_HW.cmp.cbp
.........\..\SDRAM_HR_HW.tiscmp.slow_1200mv_85c.ddb
.........\..\SDRAM_HR_HW.asm.qmsg
.........\..\cntr_78j.tdf
.........\..\cntr_5fi.tdf
.........\..\SDRAM_HR_HW.cmp.bpm
.........\..\SDRAM_HR_HW.sta.qmsg
.........\..\SDRAM_HR_HW.cmp.ecobp
.........\..\SDRAM_HR_HW.tis_db_list.ddb
.........\..\cmpr_ifc.tdf
.........\..\cntr_p1j.tdf
.........\..\prev_cmp_SDRAM_HR_HW.map.qmsg
.........\..\cmpr_efc.tdf
.........\..\SDRAM_HR_HW.tiscmp.fast_1200mv_0c.ddb
.........\..\prev_cmp_SDRAM_HR_HW.fit.qmsg
.........\..\prev_cmp_SDRAM_HR_HW.asm.qmsg
.........\..\SDRAM_HR_HW.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
.........\..\SDRAM_HR_HW.sld_design_entry.sci
.........\..\prev_cmp_SDRAM_HR_HW.sta.qmsg
.........\..\SDRAM_HR_HW.map.qmsg
.........\..\SDRAM_HR_HW.hier_info
.........\..\decode_4uf.tdf
.........\..\SDRAM_HR_HW.sgdiff.cdb
.........\..\SDRAM_HR_HW.sta.rdb
.........\..\SDRAM_HR_HW.syn_hier_info
.........\..\SDRAM_HR_HW.map.ecobp
.........\..\SDRAM_HR_HW.map.kpt
.........\..\SDRAM_HR_HW.cmp_merge.kpt
.........\..\SDRAM_HR_HW.cmp.kpt
.........\..\SDRAM_HR_HW.tan.qmsg
.........\..\SDRAM_HR_HW.map_bb.cdb
.........\..\SDRAM_HR_HW.map_bb.hdb
.........\..\SDRAM_HR_HW.map.logdb
.........\..\SDRAM_HR_HW.map.bpm
.........\..\SDRAM_HR_HW.asm_labs.ddb
.........\..\SDRAM_HR_HW.asm.rdb
.........\..\SDRAM_HR_HW.sta_cmp.6_slow_1200mv_85c.tdb
.........\..\SDRAM_HR_HW.cmp.hdb
.........\..\SDRAM_HR_HW.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.........\..\SDRAM_HR_HW.tiscmp.slow_1200mv_0c.ddb
.........\..\SDRAM_HR_HW.cmp.rdb
.........\..\SDRAM_HR_HW.rpp.qmsg
.........\..\SDRAM_HR_HW.sgate.rvd
.........\..\SDRAM_HR_HW.sgate_sm.rvd
.........\..\prev_cmp_SDRAM_HR_HW.tan.qmsg
.........\SDRAM_HR_HW.qsf.bak
.........\SDRAM_HR_HW.done
.........\SDRAM_HR_HW.dpf
.........\SDRAM_HR_HW.pin
.........\SDRAM_HR_HW.pof
.........\SDRAM_HR_HW.qpf
.........\SDRAM_HR_HW.qsf
.........\SDRAM_HR_HW.fit.smsg
.........\SDRAM_HR_HW.map.smsg
.........\SDRAM_HR_HW.sof
.........\SDRAM_HR_HW.fit.summary
.........\SDRAM_HR_HW.map.summary
.........\SDRAM_HR_HW.tan.summary
.........\SDRAM_HR_HW_assignment_defaults.qdf

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