VHDL-FPGA-Verilog List Page 240

VHDL-FPGA-Verilog list

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adaptive_lms_equalizer Downloaded：0: The adaptive algorithm verilog implementation is a good example of learning
Date : 2025-05-25 Size : 55kb User : lionsde
dds_synthesizer Downloaded：0: Verilog prepared by the DDS-based signal generator, the frequency variable.
Date : 2025-05-25 Size : 325kb User : lionsde
PllTwoOrder Downloaded：0: Verilog prepared by the second-order phase-locked loop code, the loop can converge.
Date : 2025-05-25 Size : 16.17mb User : lionsde
E8_1_RS232 Downloaded：0: VHDL prepared by the RS232 serial communication code, you can use.
Date : 2025-05-25 Size : 745kb User : lionsde
E7_2_IntBitSync Downloaded：0: Bit synchronization of the VHDL implementation, the code can be integrated. very useful!
Date : 2025-05-25 Size : 1.1mb User : lionsde
Mtk_Res1.4 Downloaded：0: mn mnbmnbmnbmbmnbmb
Date : 2025-05-25 Size : 199kb User : osamai
mingmie-V4.1 Downloaded：0: Based on the time delay estimation of power spectrum, Based on piecewise nonlinear weight value Pso algorithm, Machine learning routines.
Date : 2025-05-25 Size : 6kb User : pjirjjmr
AD6.9常用元器件封装库 Downloaded：0: PCB common original libraryCB commonly used original library, commonly used not commonly used, Ad9 and AD6 use decompression. Oh, just look at everyone
Date : 2025-05-25 Size : 398kb User : 反对
交通灯 Downloaded：0: this is a simple-traffic-light
Date : 2025-05-25 Size : 17kb User : xiuping
UART Downloaded：0: Verilog io analog serial port, using io simulation UART serial communication, no hardware serial port
Date : 2025-05-25 Size : 1.22mb User : yt14212
cordic Downloaded：0: The verilog implementation of CORDIC algorithm is suitable for learning.
Date : 2025-05-25 Size : 6.63mb User : yt14212
97957700spi Downloaded：0: Own serial test procedures, validation, and very complete. For your reference use
Date : 2025-05-25 Size : 5kb User : wspudhy

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