VHDL-FPGA-Verilog List Page 239

VHDL-FPGA-Verilog list

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verilog_PLL Downloaded：0: All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simulation.
Date : 2025-05-25 Size : 11kb User : 小米1
Zet-1.3.1 Downloaded：0: ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 interface .
Date : 2025-05-25 Size : 2.37mb User : VectorIII
sp6 Downloaded：0: Using, a company developed by FPGA, is a LED running water lamp program.
Date : 2025-05-25 Size : 109kb User : xshtx
vga_top2 Downloaded：0: EDA class set in the VGA display, containing the source code and the entire project various documents
Date : 2025-05-25 Size : 9.42mb User : migamigamiga
FIFO_ASY Downloaded：0: Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.
Date : 2025-05-25 Size : 2kb User : 253765952
按键控制led Downloaded：0: Press button to control the LED lights on and off
Date : 2025-05-25 Size : 4.95mb User : baby321
fir Downloaded：0: Power filter is composed of capacitance and inductance and resistance of filter circuit.Specific frequency of the filter to the power cord or the point that the frequency of frequency effectively filter out, get a specif
Date : 2025-05-25 Size : 7kb User : 6Andd7
序列检测器 Downloaded：0: This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010
Date : 2025-05-25 Size : 18kb User : 不唯花开
code.sources Downloaded：0: zcscscsasfsdfsfasfasf
Date : 2025-05-25 Size : 3kb User : 辕门暮雪
RS_422 Downloaded：0: On the K7FPGA, using Verilog language RS422 serial port, because did not find Verilog, so chose VHDL
Date : 2025-05-25 Size : 5.61mb User : allen3zsy
Verilog HDL（第4版）[王金明][电子教案] Downloaded：0: Verilog HDL (Fourth Edition) [] [Wang Jinming].rar e-lesson plans note ppt plans.
Date : 2025-05-25 Size : 5.18mb User : lart
src Downloaded：0: user FPGA and DAC generate DDS
Date : 2025-05-25 Size : 29kb User : WOO8

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