VHDL-FPGA-Verilog List Page 236

VHDL-FPGA-Verilog list

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Contador Downloaded：0: counter project developed on the universuty
Date : 2025-08-19 Size : 45kb User : diegorezek
TrablholastPSD Downloaded：0: digital 24h clock on ise
Date : 2025-08-19 Size : 415kb User : diegorezek
Aula_4 Downloaded：0: ise project on class
Date : 2025-08-19 Size : 262kb User : diegorezek
a1Aula6 Downloaded：0: aula de projeto de sistemas digitais
Date : 2025-08-19 Size : 683kb User : diegorezek
TrabPrat_70889 Downloaded：0: exemplo codigo vhdl no ise
Date : 2025-08-19 Size : 864kb User : diegorezek
CorrecaoProva2 Downloaded：0: correction of test vhdl on ise
Date : 2025-08-19 Size : 669kb User : diegorezek
a2Aula6 Downloaded：0: classe exerciceses of vhdl
Date : 2025-08-19 Size : 20kb User : diegorezek
test_ADDA_sin Downloaded：0: Sinusoidal signal generator, ADDA conversion, microcontroller programming
Date : 2025-08-19 Size : 3.75mb User : 林代码
mdio Downloaded：0: the code of mdio,including reading and writing the code of mdio
Date : 2025-08-19 Size : 1kb User : bijuan
8位数字显示的简易频率计 Downloaded：0: A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the circuit is 1HZ, and the measured value is output in the form of 8421BCD code; (3) the system has a reset key; (4) adopt the method
Date : 2025-08-19 Size : 92kb User : 浅月紫竹林
mips Downloaded：0: use the verilog language to programme the CPU
Date : 2025-08-19 Size : 4kb User : 光亮
公交报站 Downloaded：0: Simple bus stop program, the use of Verilog HDL language
Date : 2025-08-19 Size : 109kb User : bearlily1314

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