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VHDL-FPGA-Verilog list
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The frequency division of the clock signal in the FPGA is used as the reference frequency, the other frequency is used as input, and the input frequency is displayed in the digital tube.
Date : 2025-05-25 Size : 8.04mb User : 狄克推多

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Implementation of IIC protocol in Verilog language
Date : 2025-05-25 Size : 1kb User : 小黑93

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count from 0 to 9,and the lum become more and more high
Date : 2025-05-25 Size : 1.29mb User : Eris

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my English very bad,so I don't write
Date : 2025-05-25 Size : 27kb User : 山雨林

systemverilog verification methodology
Date : 2025-05-25 Size : 43.68mb User : 影魅

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arithmetic and logic unit
Date : 2025-05-25 Size : 1kb User : 请问让人讨厌

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FPGA serial communication, in the realization of character data transmission, and STM32 serial communication similar
Date : 2025-05-25 Size : 3.2mb User : helmess

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4LED water lamp program, you can change the frequency. Using state machine, low level active light, high level extinction
Date : 2025-05-25 Size : 1kb User : 柳弦

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Seven segment digital decoder, 0~9 can display a total of 10 characters.
Date : 2025-05-25 Size : 432kb User : Stella\

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Clock, with alarm set, the whole point timekeeping function, alarm clock with stop button
Date : 2025-05-25 Size : 716kb User : nexr

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vga is in the platform of fpga
Date : 2025-05-25 Size : 1kb User : TonyTom

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Many versions of the original download were not available. This version is available
Date : 2025-05-25 Size : 760kb User : liuyijian
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