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Based on mx11046 nios2 system initialization, sampling, write commands, read data, and some optimization Settings
Date : 2025-08-18 Size : 2kb User : yanbo

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Based on dac8532 nios2 system initialization, write command, write data, read data, and some optimization operation
Date : 2025-08-18 Size : 1kb User : yanbo

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Based on lm75 nios2 system initialization, write command, write data, read data, and some optimization operation
Date : 2025-08-18 Size : 1kb User : yanbo

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Based on the iic nios2 system initialization, write command, write data, read data, and some optimization operation
Date : 2025-08-18 Size : 3kb User : yanbo

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Waveform acquisition sample source code, compiled by the Quartus II 9.1 SP2 environment.
Date : 2025-08-18 Size : 1.24mb User : Henry

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Ordinary data transmission source, using SRAM virtual FIFO data cache. The virtual FIFO only the external data uploaded to the computer data cache.
Date : 2025-08-18 Size : 1.35mb User : Henry

Digital frequency counter, the measured input signal: square wave, the test frequency range: 10Hz to 100MHz
Date : 2025-08-18 Size : 5.51mb User : 宋世湃

The stepper motor Verilog language control program, simple and practical
Date : 2025-08-18 Size : 389kb User : 王晓伟

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" Xilinx ISE 9.X FPGA/CPLD Design Guide to FPGA/CPLD design process as the main line, elaborated on the use of ISE Integrated Development Environment, and provides several examples will be described. Book on the basi
Date : 2025-08-18 Size : 4.58mb User : starcool

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IIC memory read and write control AT24C02 read and write control
Date : 2025-08-18 Size : 3kb User : 王磊

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Altera DE2 development board CD-ROM, code, documentation, manuals, full-Oh!
Date : 2025-08-18 Size : 16.28mb User : wangbo

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Xilinx FPGA timing constraint information, original, classic no reason
Date : 2025-08-18 Size : 2.22mb User : wangbo
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