VHDL-FPGA-Verilog List Page 1103

VHDL-FPGA-Verilog list

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dtrigger Downloaded：0: In the Quartus software using the Verilog HDL prepared D flip-flop the source code
Date : 2025-08-18 Size : 2kb User : 徐鑫
vclkdiv Downloaded：0: With in QuartusII software written in Verilog HDL source code of the divider
Date : 2025-08-18 Size : 2kb User : 徐鑫
ji_shu_qi Downloaded：0: Verilog HDL prepared counter with in QuartusII software source code
Date : 2025-08-18 Size : 5kb User : 徐鑫
shift_register Downloaded：0: The source code of the shift register in QuartusII software using Verilog HDL prepared
Date : 2025-08-18 Size : 3kb User : 徐鑫
RS_bmq Downloaded：0: The RS encoder Verilog HDL prepared with in QuartusII software source code
Date : 2025-08-18 Size : 15kb User : 徐鑫
MotorVHDL Downloaded：2: VHDL program a Panasonic servo motor drive and feedback
Date : 2025-08-18 Size : 4kb User : hlt
keshe Downloaded：0: Low-pass filter, based on the the EDA use VHDL language digital filtering function
Date : 2025-08-18 Size : 1kb User : 候金成
test12 Downloaded：0: Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been tested (in development environment I did not find VerilogHDL, we chose
Date : 2025-08-18 Size : 1kb User : 潘昕
i2c Downloaded：0: I2C bus has been verified, including ModelSim files
Date : 2025-08-18 Size : 202kb User : honglei
20130517 Downloaded：0: Cpld control ads8364 six-channel sampling, using the Verilog language
Date : 2025-08-18 Size : 1kb User : hua
src Downloaded：0: 12 seconds timing control circuit: When the 12 seconds when the timer expires, the indicator goes off L1 L2 indicator flashes 5 times per second speed.
Date : 2025-08-18 Size : 4kb User : 自行车
led_cycle Downloaded：0: Figure running water light
Date : 2025-08-18 Size : 199kb User : 柳炳琦

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