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VHDL-FPGA-Verilog list
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shixusuccessful
Downloaded:0
Simulation time division multiplexing communication system
Date
: 2025-08-18
Size
: 574kb
User
:
齐伟利
DCO_ST
Downloaded:0
Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
Date
: 2025-08-18
Size
: 1kb
User
:
刘超
MDIO
Downloaded:0
The register communication protocol Verilog description of the network PHY88E1111 lookback can read the PHY data
Date
: 2025-08-18
Size
: 1kb
User
:
tianfuhe
DPLL_TEST
Downloaded:0
Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
Date
: 2025-08-18
Size
: 1kb
User
:
刘超
gen_clk
Downloaded:0
A variable duty cycle signal generator
Date
: 2025-08-18
Size
: 1kb
User
:
刘超
fpga_GRT
Downloaded:0
PWM signal generator, adjust the frequency bandwidth of 30M, 0.02 of the duty cycle can be adjusted accuracy
Date
: 2025-08-18
Size
: 10.55mb
User
:
曹亮亮
Golf_Test
Downloaded:0
Verilog language golf simulator under-bit machine detection parameters include speed, elevation and declination.
Date
: 2025-08-18
Size
: 20.28mb
User
:
孙尚超
seg7
Downloaded:0
Verilog language, showing seven-segment LED display correctly, cycloneI
Date
: 2025-08-18
Size
: 2kb
User
:
郭建成
EDA
Downloaded:0
The VHDL language the traffic lights. There is a program to the circuit diagram.
Date
: 2025-08-18
Size
: 27.5mb
User
:
阎晓宁
clock-pro
Downloaded:0
A verilog prepared in the classic clock program, easy to use, and to share with you!
Date
: 2025-08-18
Size
: 371kb
User
:
李鹏飞
h_adder
Downloaded:0
Half adder VHDL code, including all documents, clearer
Date
: 2025-08-18
Size
: 107kb
User
:
徐威威
src
Downloaded:0
n-bit binary absolute value subtraction, FPGA-based hardware language
Date
: 2025-08-18
Size
: 4kb
User
:
韩凯
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