VHDL-FPGA-Verilog List Page 1109

VHDL-FPGA-Verilog list

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BCD Downloaded：0: Using Verilog HDL language implementation of BCD addition
Date : 2025-08-18 Size : 40kb User : 姚远
TWO Downloaded：0: Using Verilog HDL language implementation public expression cross coefficient filter
Date : 2025-08-18 Size : 307kb User : 姚远
cpu_cache_interrupt Downloaded：0: the CPU five water with verilog to write cache interrupt
Date : 2025-08-18 Size : 48kb User : 王久力
chenxu Downloaded：0: Verilog HDL 16 election of a data selector
Date : 2025-08-18 Size : 17kb User : hehe
clock Downloaded：0: A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies excluding state machine, easy to understand.
Date : 2025-08-18 Size : 1kb User : Welson
chenxu Downloaded：0: The use of state machine design is the sine wave signal generator:// output 4 connects a 4-bit DA converter, i.e. the 4-bit digital signal output can be directly through the DA converter to an analog signal.
Date : 2025-08-18 Size : 3kb User : hehe
chengxu Downloaded：0: Design state machine to read data from the SRAM, and added, that is seeking SRAM [7:0] [2:0] 8 bytes and output, SRAM built-in RAM
Date : 2025-08-18 Size : 3kb User : hehe
chengxu Downloaded：0: State machine reads the external RAM RAM interface OE Output Enable WR, low-level to write RAM AB [7:0] address bus DB [7:0] address bus// RAM 0 to 127 data read-out and phase plus the final result is stored in the addre
Date : 2025-08-18 Size : 3kb User : hehe
text_fir_lbq Downloaded：0: A module in my thesis, I finite length FIR filters can be directly compiled simulation download. . The actual test are available. .
Date : 2025-08-18 Size : 2.39mb User : shao
weitebi_notes Downloaded：0: Viterbi decoding, a more detailed description
Date : 2025-08-18 Size : 4kb User : 王一凡
shuzishizong Downloaded：0: Digital clock alarm clock is adjustable
Date : 2025-08-18 Size : 928kb User : 小白菜
jiaotongdeng Downloaded：0: State machine to achieve the crossroads of traffic lights red yellow and green code with eight high three LED lights denote a junction of red, yellow, and green the lower three b junction of red yellow and green
Date : 2025-08-18 Size : 427kb User : 小白菜

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