VHDL-FPGA-Verilog List Page 1100

VHDL-FPGA-Verilog list

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clock_seg Downloaded：0: FPGA divide a sometimes every minute clock, and digital display
Date : 2025-08-18 Size : 3.22mb User : mingzhanghui
rx_tx Downloaded：0: Host computer and the FPGA RS232 communication, the FPGA can send and receive.
Date : 2025-08-18 Size : 3.1mb User : mingzhanghui
lcd Downloaded：0: FPGA control word written on the LCD screen, and displayed on the LCD screen a string This is a test
Date : 2025-08-18 Size : 3.03mb User : mingzhanghui
seven_color Downloaded：0: FPGA generate seven vertical color bar are seven basic colors. And display monitor to the VGA port
Date : 2025-08-18 Size : 3.26mb User : mingzhanghui
div_clk Downloaded：0: A 20M to 16M clock frequency applet. There are some loopholes Please correct itself
Date : 2025-08-18 Size : 1kb User : yang
pri_encoder_using_if Downloaded：0: encoder using if - verilog
Date : 2025-08-18 Size : 1kb User : amin
decoder_using_with Downloaded：0: decoder_using_with verilog code
Date : 2025-08-18 Size : 1kb User : amin
EDA Downloaded：0: 4 decimal counter+7 of segment LED display
Date : 2025-08-18 Size : 663kb User : 陈旭纯
cpu Downloaded：0: Use VHDL to write a cpu program that can run on the bench run, including a variety of basic addressing modes, which also contains the waveform of each module
Date : 2025-08-18 Size : 2.35mb User : sherrytonger
vgachar Downloaded：0: Within the FPGA to generate a character video and VGA display to display.
Date : 2025-08-18 Size : 1.59mb User : mingzhanghui
clock_seg Downloaded：0: FPGA divide a sometimes every minute clock, and digital display
Date : 2025-08-18 Size : 3.22mb User : mingzhanghui
rx_tx Downloaded：0: Host computer and the FPGA RS232 communication, the FPGA can send and receive.
Date : 2025-08-18 Size : 3.1mb User : mingzhanghui

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