Half adder VHDL code, including all documents, clearer

h_adder
.......\db
.......\..\h_adder.asm.qmsg
.......\..\h_adder.cbx.xml
.......\..\h_adder.cmp.cdb
.......\..\h_adder.cmp.hdb
.......\..\h_adder.cmp.kpt
.......\..\h_adder.cmp.logdb
.......\..\h_adder.cmp.rdb
.......\..\h_adder.cmp.tdb
.......\..\h_adder.cmp0.ddb
.......\..\h_adder.db_info
.......\..\h_adder.dbp
.......\..\h_adder.eco.cdb
.......\..\h_adder.eds_overflow
.......\..\h_adder.fit.qmsg
.......\..\h_adder.hier_info
.......\..\h_adder.hif
.......\..\h_adder.map.cdb
.......\..\h_adder.map.hdb
.......\..\h_adder.map.logdb
.......\..\h_adder.map.qmsg
.......\..\h_adder.pre_map.cdb
.......\..\h_adder.pre_map.hdb
.......\..\h_adder.psp
.......\..\h_adder.pss
.......\..\h_adder.rtlv.hdb
.......\..\h_adder.rtlv_sg.cdb
.......\..\h_adder.rtlv_sg_swap.cdb
.......\..\h_adder.sgdiff.cdb
.......\..\h_adder.sgdiff.hdb
.......\..\h_adder.signalprobe.cdb
.......\..\h_adder.sim.hdb
.......\..\h_adder.sim.qmsg
.......\..\h_adder.sim.rdb
.......\..\h_adder.sim.vwf
.......\..\h_adder.sld_design_entry.sci
.......\..\h_adder.sld_design_entry_dsc.sci
.......\..\h_adder.syn_hier_info
.......\..\h_adder.tan.qmsg
.......\..\wed.zsf
.......\h_adder.asm.rpt
.......\h_adder.bdf
.......\h_adder.bsf
.......\h_adder.done
.......\h_adder.fit.rpt
.......\h_adder.fit.smsg
.......\h_adder.fit.summary
.......\h_adder.flow.rpt
.......\h_adder.map.rpt
.......\h_adder.map.summary
.......\h_adder.pin
.......\h_adder.pof
.......\h_adder.qpf
.......\h_adder.qsf
.......\h_adder.qws
.......\h_adder.sim.rpt
.......\h_adder.sof
.......\h_adder.tan.rpt
.......\h_adder.tan.summary
.......\h_adder.vwf

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