Altera DE2 development board CD-ROM, code, documentation, manuals, full-Oh!

Altera DE2教程和实验练习(English)\Altera 调试客户端\altera_monitor_program_setup.zip
.................................\.................\教程(tut_Altera_Monitor_Program).pdf
.................................\数字逻辑实验练习\实验 6 加法器 减法器和乘法器(lab6_Verilog).pdf
.................................\................\实验 6 加法器 减法器和乘法器(lab6_VHDL).pdf
.................................\................\实验 6 加法器 减法器和乘法器2(lab6_Verilog).pdf
.................................\................\实验 6 加法器 减法器和乘法器2(lab6_VHDL).pdf
.................................\................\实验 8 存储器块(lab8_Verilog).pdf
.................................\................\实验 8 存储器块(lab8_VHDL).pdf
.................................\................\实验 8 存储器块2(lab8_Verilog).pdf
.................................\................\实验 8 存储器块2(lab8_VHDL).pdf
.................................\................\实验 9 一个简单的处理器(lab9_Verilog).pdf
.................................\................\实验 9 一个简单的处理器(lab9_VHDL).pdf
.................................\................\实验 9 一个简单的处理器2(lab9_Verilog).pdf
.................................\................\实验 9 一个简单的处理器2(lab9_VHDL).pdf
.................................\................\实验 1 开关 灯和复用器(lab1_Verilog).pdf
.................................\................\实验 1 开关 灯和复用器(lab1_VHDL).pdf
.................................\................\实验 1 开关 灯和复用器2(lab1_Verilog).pdf
.................................\................\实验 1 开关 灯和复用器2(lab1_VHDL).pdf
.................................\................\实验 10 增强处理器(lab10_Verilog).pdf
.................................\................\实验 10 增强处理器(lab10_VHDL).pdf
.................................\................\实验 10 增强处理器2(lab10_Verilog).pdf
.................................\................\实验 10 增强处理器2(lab10_VHDL).pdf
.................................\................\实验 2 数字和显示(lab2_Verilog).pdf
.................................\................\实验 2 数字和显示(lab2_VHDL).pdf
.................................\................\实验 2 数字和显示2(lab2_Verilog).pdf
.................................\................\实验 2 数字和显示2(lab2_VHDL).pdf
.................................\................\实验 3 锁存器 触发器和寄存器(lab3_Verilog).pdf
.................................\................\实验 3 锁存器 触发器和寄存器(lab3_VHDL).pdf
.................................\................\实验 3 锁存器 触发器和寄存器2(lab3_Verilog).pdf
.................................\................\实验 3 锁存器 触发器和寄存器2(lab3_VHDL).pdf
.................................\................\实验 4 计数器(lab4_Verilog).pdf
.................................\................\实验 4 计数器(lab4_VHDL).pdf
.................................\................\实验 4 计数器2(lab4_Verilog).pdf
.................................\................\实验 4 计数器2(lab4_VHDL).pdf
.................................\................\实验 5 时钟和定时器(lab5_Verilog).pdf
.................................\................\实验 5 时钟和定时器(lab5_VHDL).pdf
.................................\................\实验 5 时钟和定时器2(lab5_Verilog).pdf
.................................\................\实验 5 时钟和定时器2(lab5_VHDL).pdf
.................................\................\实验 7 有限状态机(lab7_Verilog).pdf
.................................\................\实验 7 有限状态机(lab7_VHDL).pdf
.................................\................\实验 7 有限状态机2(lab7_Verilog).pdf
.................................\................\实验 7 有限状态机2(lab7_VHDL).pdf
.................................\........教程\DE2-DE1电路板入门(tut_initialDE1).pdf
.................................\............\DE2-DE1电路板入门(tut_initialDE2).pdf
.................................\............\Quartus II 仿真(tut_simulation_verilog).pdf
.................................\............\Quartus II 仿真(tut_simulation_vhdl).pdf
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