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shixusuccessful

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-05-17
  • Size : 574kb
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  • Author :齐****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Simulation time division multiplexing communication system
Packet file list
(Preview for download)


shixusuccessful\fuse.log
...............\isim\isim.tmp_save\_1
...............\....\isimcrash.log
...............\....\simulate_dofile.log
...............\....\simulate_dofile.log_back
...............\....\work\shixu.vdb
...............\....\....\shixusuccessful.vdb
...............\....\_tmp\ieee\p_0017514958.didat
...............\....\....\....\p_0774719531.didat
...............\....\....\....\p_1242562249.didat
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...............\....\....\.......\a_3449594526_2431929443.didat
...............\....\....\.......\a_3452876758_19579
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