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[VHDL-FPGA-Verilog] RC5-VHDL

Description: RC5 encryption algorithm In VHDL
Platform: | Size: 10240 | Author: siavosh | Hits:

[VHDL-FPGA-Verilog] 3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r

Description: Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
Platform: | Size: 147456 | Author: T. H. Sutikno | Hits:

[VHDL-FPGA-Verilog] VHDL--testbench

Description: VHDL 的testbench 编写风格及技巧，有助利用modelsim做仿真，一看就会！-The testbench VHDL writing style and skills will help make using modelsim simulation, a look will be!
Platform: | Size: 227328 | Author: 陈华 | Hits:

[VHDL-FPGA-Verilog] VHDL-Xilinx-ISE-a-ModelSim

Description: VHDL上机手册（基于Xilinx ISE & ModelSim）-VHDL-on manual (based on the Xilinx ISE & ModelSim)
Platform: | Size: 831488 | Author: l | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: This ebook introduces the basic use of VHDL.It provides lots of codings,you can make use of it.
Platform: | Size: 6426624 | Author: huli | Hits:

[VHDL-FPGA-Verilog] simulink-matlab-to-vhdl

Description: convert matlab and simulink files to vhdl
Platform: | Size: 181248 | Author: tatta | Hits:

[USB develop] USB-1.1-IP-CORE-VHDL

Description: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Platform: | Size: 425984 | Author: sxhfjgl010 | Hits:

[VHDL-FPGA-Verilog] Meter-VHDL-code

Description: 基于FPGA的计价器系统 FPGA；VHDL语言；出租车计价器-The Meter Design Based on FPGA FPGA VHDL Language Taxi meter
Platform: | Size: 2048 | Author: myblues | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-infrared-remote-audio

Description: 基于FPGA和VHDL的红外遥控音响的原理图+PCB+收发源程序-FPGA and VHDL-based infrared remote audio transceiver schematic+ PCB+ source
Platform: | Size: 242688 | Author: bsyy | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 各种基本的VHDL实例，可以用来参考学习，希望能够帮到大家！-Examples of the basic VHDL can be used to refer to learning, want to help everyone!
Platform: | Size: 6324224 | Author: 吴斌 | Hits:

[VHDL-FPGA-Verilog] RC6-block-cipher-using-VHDL

Description: VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped
Platform: | Size: 55296 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] HASH-code-implementation-using-VHDL

Description: implementation for Secure Hash Algorithm 1 SHA-1 in vhdl language contain no test file.
Platform: | Size: 14336 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] Part-1-DWT-haar-using-VHDL

Description: Part 1 implementation of Discrete wavelet transform in VHDL language Haar Filter
Platform: | Size: 17408 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] Part-2-DWT-haar-using-VHDL

Description: Part 2 testbench for Discrete wavelet transfrom implementation in VHDL language Haar Filter
Platform: | Size: 13312 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] vhdl-implementation-of-huffman-algorithm

Description: VHDL implementation of HUFFMAN algorithm
Platform: | Size: 5120 | Author: anu | Hits:

[VHDL-FPGA-Verilog] VHDL-source-code

Description: 一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
Platform: | Size: 45056 | Author: yfgf | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[VHDL-FPGA-Verilog] VHDL-Made-Easy

Description: Intended for both hardware and sofware designers interested in learning VHDL.HDL (Hardware Description Languages) expertise is a critical, distinguishing skill that is essential to a successful career as an electronics designer. With the booming communications and internet market demanding better hardware, the need for sophisticated electronics designers has never been greater. This book will provide a practical HDL tutorial that goes beyond the many reference and syntax manuals that exist to demonstrate "how to" techniques.
Platform: | Size: 12593152 | Author: impavide | Hits:

[VHDL-FPGA-Verilog] aes-vhdl

Description: this file contains vhdl code for aes
Platform: | Size: 119808 | Author: baby | Hits:

[VHDL-FPGA-Verilog] spi-vhdl

Description: 用vhdl写的spi通信，arm为主设备，fpga为从设备，其中包括代码，以及具体协议-failed to translate
Platform: | Size: 258048 | Author: 欧翔 | Hits:
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