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[VHDL-FPGA-Verilog] VHDL

Description: Program VHDL is scan keypad matrix 3*3 display to LCD
Platform: | Size: 659456 | Author: pokamon | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: vhdl代码串口的实现,每个部分的代码别写好了，元件例化一下即可用，-my english is poor ,i hope this make you understand and help you this is Serial implementation vhdl Categories:hardware
Platform: | Size: 9216 | Author: hs | Hits:

[VHDL-FPGA-Verilog] VHDL-PCI

Description: PCI 源码 vhdl 非常好的东东 哈哈 -PCI vhdl very good ！ haha haha haha
Platform: | Size: 27648 | Author: 朱根生 | Hits:

[Software Engineering] 13105886-vhdl-lab-programs

Description: vhdl programme on lfsr
Platform: | Size: 289792 | Author: rahul | Hits:

[Other] Vhdl-Primer-by-Bhaskar

Description: This book, written by J. Bhaskar explains all the basic concepts of VHDL(Very High Speed Integrated Circuit Hardware Discription Language). VHDL is used to design digital logic gates on a chip. 163 Pages
Platform: | Size: 1119232 | Author: frank | Hits:

[Program doc] VHDL

Description: 本文是基于VHDL语言的洗衣机控制器设计与仿真的源代码，并且内附详细解析，对初学者有很大的帮助-This article is based on the VHDL language, washing machine controller design and simulation of the source code, and included detailed analysis, there is a great help for beginners
Platform: | Size: 258048 | Author: 段 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.
Platform: | Size: 2547712 | Author: 陈叶飞 | Hits:

[VHDL-FPGA-Verilog] ds18b20-vhdl

Description: vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange
Platform: | Size: 1024 | Author: yudezhao | Hits:

[Software Engineering] Cordic-VHDL

Description: Cordic算法的VHDL实现，实现了Cordic算法的过程经典-CordicVHDL
Platform: | Size: 217088 | Author: 陈好 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: （1）用VHDL语言编写程序，在EDA实验板上实现 （2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。 （3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。 用VHDL语言编写程序，在EDA实验板上实现 （4） 整点报时。 （5）. 闹钟功能。 （6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Platform: | Size: 4096 | Author: malon | Hits:

[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl)

Description: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Platform: | Size: 967680 | Author: jlz | Hits:

[Program doc] key_expansion.vhdl

Description: key expansion code for vhdl in advanced encryption standard
Platform: | Size: 2048 | Author: sruthi | Hits:

[Software Engineering] VHDL

Description: 本文介绍的是基于VHDL的简易电子琴的设计，采用EDA作为开发工具。-This article describes a simple VHDL-based keyboard design and use of EDA as a development tool.
Platform: | Size: 124928 | Author: 艾无止境 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 一本介绍VHDL的书，讲的非常详细，有大量实例，一本很不错的参考资料-A VHDL description of the book, spoke in great detail, there are a large number of instances, a very good reference for
Platform: | Size: 24856576 | Author: alvin | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
Platform: | Size: 15360 | Author: 张霄 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 利用VHDL实现任意函数发生器，包括方波、正弦波、三角波等。-The use of VHDL to achieve arbitrary function generator, including square, sine wave, triangle wave and so on.
Platform: | Size: 39936 | Author: 陈海巍 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于vhdl语言的音乐播放器的设计代码。请各位可以根据自己的需要用。-Vhdl language-based music player, the design of the code. Members can be used according to their own needs.
Platform: | Size: 89088 | Author: 赵小孩 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
Platform: | Size: 1024 | Author: wu | Hits:

[Books] VHDL

Description: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. -A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
Platform: | Size: 7168 | Author: Michael Lee | Hits:
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